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Content Provider | ACM Digital Library |
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Author | Benini, Luca Gupta, Rajesh K. Rahimi, Abbas |
Abstract | This paper proposes a new model of functional units for variation-induced timing errors due to PVT variations and device Aging (PVTA). The model takes into account PVTA parameter variations, clock frequency, and the physical details of Placed-and-Routed (P&R) functional units in 45nm TSMC analysis flow. Using this model and PVTA monitoring circuits, we propose Hierarchically Focused Guardbanding (HFG) as a method to adaptively mitigate PVTA variations. We demonstrate the effectiveness of HFG on GPU architecture at two granularities of observation and adaptation: (i) fine-grained instruction-level; and (ii) coarse-grained kernel-level. Using coarse-grained PVTA monitors with kernel-level adaptation, the throughput increases by 70% on average. By comparison, the instruction-by-instruction monitoring and adaptation enhances throughput by a factor of 1.8x-2.1x depending on the configuration of PVTA monitors and the type of instructions executed in the kernels. |
Starting Page | 1695 |
Ending Page | 1700 |
Page Count | 6 |
File Format | |
ISBN | 9781450321532 |
Language | English |
Publisher | Association for Computing Machinery (ACM) |
Publisher Date | 2013-03-18 |
Publisher Place | San Jose |
Access Restriction | Subscribed |
Subject Keyword | Pvt variation Aging Adaptive guardbanding Gpu |
Content Type | Text |
Resource Type | Article |
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