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| Content Provider | ACM Digital Library |
|---|---|
| Author | Gherman, Valentin Sarrazin, Sébastien Evain, Samuel de Barros Naviner, Lirida Alves Bonhomme, Yannick |
| Abstract | This paper presents new scan solutions with low latency overhead and on-line monitoring support. Shadow flip-flops with scan design are associated to system flip-flops in order to (a) provide concurrent delay fault detection and (b) avoid the scan chain insertion of system flip-flops. A mixed scan architecture is proposed which involves flip-flops with shadow scan design at the end of timing-critical paths and flip-flops with standard scan at non-critical locations. In order to preserve system controllability during test, system flip-flops with shadow scan can be set in scan mode and selectively reset before switching to capture mode. It is shown that shadow scan design with asynchronous set and reset may have a lower latency overhead than standard scan design. A shadow scan solution is proposed which, in addition to concurrent delay fault detection, provides simultaneous scan and capture capability. |
| Starting Page | 1077 |
| Ending Page | 1082 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781450321532 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2013-03-18 |
| Publisher Place | San Jose |
| Access Restriction | Subscribed |
| Subject Keyword | Shadow scan Dynamic variations Concurrent fault detection Delay faults Monitoring |
| Content Type | Text |
| Resource Type | Article |
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