NDLI: SlackProbe: a low overhead in situ on-line timing slack monitoring methodology

Please wait, while we are loading the content...

Smart systems for internet of things

Optimized out-of-order parallel discrete event simulation using predictions

Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors

AVICA: an access-time variation insensitive L1 cache architecture

Low complexity QR-decomposition architecture using the logarithmic number system

Reliability challenges of real-time systems in forthcoming technology nodes

Sensitivity analysis for arbitrary activation patterns in real-time systems

Modular SoC integration with subsystems: the audio subsystem case

Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead

Profit maximization through process variation aware high level synthesis with speed binning

Extracting useful computation from error-prone processors for streaming applications

SCC thermal model identification via advanced bias-compensated least-squares

MTTF-balanced pipeline design

FIFO cache analysis for WCET estimation: a quantitative approach

Role of design in multiple patterning: technology development, design enablement and process control

A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems

Reliability analysis reloaded: how will we survive?

MALEC: a multiple access low energy cache

Comprehensive analysis of software countermeasures against fault attacks

Accurate QBF-based test pattern generation in presence of unknown values

Security challenges in automotive hardware/software architecture design

Experiences with mobile processors for energy efficient HPC

Alternative power supply concepts for self-sufficient wireless sensor nodes by energy harvesting

A hybrid approach for fast and accurate trace signal selection for post-silicon debug

A cache design for probabilistically analysable real-time systems

Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array

Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA

HW-SW integration for energy-efficient/variability-aware computing

Near-threshold voltage design in nanoscale CMOS

On-the-fly verification of memory consistency with concurrent relaxed scoreboards

A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization

Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems

Energy-efficient multicore chip design through cross-layer approach

A satisfiability approach to speed assignment for distributed real-time systems

Development of low power many-core SoC for multimedia applications

Verifying safety and liveness for the FlexTM hybrid transactional memory

Dynamic configuration prefetching based on piecewise linear prediction

OAP: an obstruction-aware cache management policy for STT-RAM last-level caches

Optimal control of a grid-connected hybrid electrical energy storage system for homes

Efficient software-based fault tolerance approach on multicore platforms

From embedded multi-core SoCs to scale-out processors

UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency

Optimized scheduling of multi-IMA partitions with exclusive region for synchronized real-time multi-core systems

Minimization of P-circuits using Boolean relations

Exploring topologies for source-synchronous ring-based network-on-chip

Designing tightly-coupled extension units for the STxP70 processor

Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels

Control-quality driven design of cyber-physical systems with robustness guarantees

Qualification and testing process to implement anti-counterfeiting technologies into IC packages

Sustainable energy policies: research challenges and opportunities

Analytical timing estimation for temporally decoupled TLMs considering resource conflicts

A sub-μa power management circuit in 0.18μm CMOS for energy harvesters

Sparse-rotary oscillator array (SROA) design for power and skew reduction

Is split manufacturing secure?

Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling

Architecture and optimal configuration of a real-time multi-channel memory controller

Roadmap towards ultimately-efficient zeta-scale datacenters

On the use of GP-GPUs for accelerating compute-intensive EDA applications

Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits

GLA: gate-level abstraction revisited

A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks

On-line functionally untestable fault identification in embedded processor cores

Game-theoretic analysis of decentralized core allocation schemes on many-core systems

Panel: "will 3D-IC remain a technology of the future... even in the future?"

Dr. Frankenstein's dream made possible: implanted electronic devices

Share with care: a quantitative evaluation of sharing approaches in high-level synthesis

DeBAR: deflection based adaptive router with minimal buffering

System-level modeling of energy in TLM for early validation of power and thermal management

Communication and migration energy aware design space exploration for multicore systems with intermittent faults

Placement optimization of power supply pads based on locality

Impact of adaptive voltage scaling on aging-aware signoff

Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools

Interactions of large scale EV mobility and virtual power plants

A new paradigm for trading off yield, area and performance to enhance performance per wafer

Shared memory aware MPSoC software deployment

A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory

Co-synthesis of data paths and clock control paths for minimum-period clock gating

Fast and efficient lagrangian relaxation-based discrete gate sizing

Closed-loop control for power and thermal management in multi-core processors: formal methods and industrial practice

Creating a sustainable information and communication infrastructure

Parallel programming with SystemC for loosely timed models: a non-intrusive approach

Energy optimization with worst-case deadline guarantee for pipelined multiprocessor systems

Dual-addressing memory architecture for two-dimensional memory access patterns

Perceptual quality preserving SRAM architecture for color motion pictures

PT-AMC: integrating preemption thresholds into mixed-criticality scheduling

Configurability in IP subystems: baseband examples

Instruction-set extension under process variation and aging effects

Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs

Efficient variation-aware statistical dynamic timing analysis for delay test applications

Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems

Overcoming post-silicon validation challenges through quick error detection (QED)

SMART: a single-cycle reconfigurable NoC for SoC applications

TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems

An EDA-friendly protection scheme against side-channel attacks

Test solution for data retention faults in low-power SRAMs

What designs for coming supercomputers?

Adaptable, high performance energy harvesters: can energy harvesting deliver enough power for automotive electronics?

Machine learning-based anomaly detection for post-silicon bug diagnosis

MARTHA: architecture for control and emulation of power electronics and smart grid systems

Variation-tolerant OpenMP tasking on tightly-coupled processor clusters

Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips

Sequentially constructive concurrency: a conservative extension of the synchronous model of computation

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs

Fast cache simulation for host-compiled simulation of embedded software

Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding

A work-stealing scheduling framework supporting fault tolerance

Breaking the energy barrier in fault-tolerant caches for multicore systems

Data mining MPSoC simulation traces to identify concurrent memory access patterns

SoC low-power practices for wireless applications

QF BV model checking with property directed reachability

An automatic tool flow for the combined implementation of multi-mode circuits

STT-RAM designs supporting dual-port accesses

Radar signature in multiple target tracking system for driver assistant application

Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors

Wireless interconnect for board and chip level

Quality-aware media scheduling on MPSoC platforms

Intuitive ECO synthesis for high performance circuits

Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach

A fast and accurate methodology for power estimation and reduction of programmable architectures

LFSR seed computation and reduction using SMT-based fault-chaining

Compositional analysis of switched ethernet topologies

Anti-counterfeiting with hardware intrinsic security

Self-aware cyber-physical systems and applications in smart buildings and cities

Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking

Saliency aware display power management

Reversible logic synthesis of k-input, m-output lookup tables

Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost

Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling

Holistic design parameter optimization of multiple periodic resources in hierarchical scheduling

Correlation-aware virtual machine allocation for energy-efficient datacenters

Enhancing multicore reliability through wear compensation in online assignment and scheduling

Lemma localization: a practical method for downsizing SMT-interpolants

Reachability analysis of nonlinear analog circuits through iterative reachable set reduction

Capturing vulnerability variations for register files

Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters

Addressing the healthcare cost dilemma by managing health instead of managing illness: an opportunity for wearable wireless sensors

FPGA latency optimization using system-level transformations and DFG restructuring

Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis

System-level modeling and microprocessor reliability analysis for backend wearout mechanisms

40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS

GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects

A parallel fast transform-based preconditioning approach for electrical-thermal co-simulation of power delivery networks

Innovative energy storage solutions for future electromobility in smart cities

Leveraging variable function resilience for selective software reliability on unreliable hardware

Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems

Systematic design of nanomagnet logic circuits

Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write $V_{MIN}$

Slack budgeting and slack to length converting for multi-bit flip-flop merging

Enhanced metamodeling techniques for high-dimensional IC design estimation problems

Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems

Self-adaptive hybrid dynamic power management for many-core systems

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores

Parameterized area-efficient multi-standard turbo decoder

An elastic mixed-criticality task model and its scheduling algorithm

Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples

Multispeculative additive trees in high-level synthesis

Memory array protection: check on read or check on write?

Design of low energy, high performance synchronous and asynchronous 64-point FFT

SlackProbe: a low overhead in situ on-line timing slack monitoring methodology

Bounding SDRAM interference: detailed analysis vs. latency-rate analysis

Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS

Switch folding: network-on-chip routers with time-multiplexed output ports

DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems

Design and implementation of a group-based RO PUF

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths

Energy-efficient in-memory database computing

Ultra-low power: an EDA challenge

Space sensitive cache dumping for post-silicon validation

Conservative open-page policy for mixed time-criticality memory controllers

Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design

Fault analysis and simulation of large scale industrial mixed-signal circuits

Fast and accurate cache modeling in source-level simulation of embedded software

Carbon nanotube circuits: opportunities and challenges

A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations

Improving simulation speed and accuracy for many-core embedded platforms with ensemble models

A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis

Testing for SoCs with advanced static and dynamic power-management capabilities

Model-based energy optimization of automotive control systems

3D integration for power-efficient computing

A semi-canonical form for sequential AIGs

Support for dynamic issue width in VLIW processors using generic binaries

Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer

Development of a fully implantable recording system for ECoG signals

Low cost permanent fault detection using ultra-reduced instruction set co-processors

Future memory and interconnect technologies

Priority assignment for event-triggered systems using mathematical programming

Retiming for Soft Error Minimization Under Error-Latching Window Constraints

Sensor-wise methodology to face NBTI stress of NoC buffers

A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection

Supervisor synthesis for controller upgrades

Perpetual and low-cost power meter for monitoring residential and industrial appliances

Toward polychronous analysis and validation for timed software architectures in AADL

Active-mode leakage reduction with data-retained power gating

3D-MMC: a modular 3D multi-core architecture with efficient resource pooling

High-sensitivity hardware trojan detection using multimodal characterization

Metastability challenges for 65nm and beyond: simulation and measurements

Robust and extensible task implementations of synchronous finite state machines

Resource efficient computing for warehouse-scale datacenters

NUMANA: a hybrid numerical and analytical thermal simulator for 3-D ICs

Core minimization in SAT-based abstraction

Formal verification of analog circuit parameters across variation utilizing SAT

Error detection in ternary CAMs using bloom filters

ARTM: a lightweight fork-join framework for many-core embedded systems

Electronic implants: power delivery and management

A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation

Topology-agnostic fault-tolerant NoC routing method

Automatic success tree-based reliability analysis for the consideration of transient and permanent faults

3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors

Periodic jitter and bounded uncorrelated jitter decomposition using incoherent undersampling

Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging

Automotive ethernet: in-vehicle networking and smart mobility

Optimization of secure embedded systems with dynamic task sets

A spectral clustering approach to application-specific network-on-chip synthesis

Defect-tolerant logic hardening for crossbar-based nanosystems

DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes

Area optimization on fixed analog floorplans using convex area functions

Sub-quadratic objectives in quadratic placement

Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm

SmartCap: user experience-oriented power adaptation for smartphone's application processor

Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

An H.264 Quad-FullHD low-latency intra video encoder

An open platform for mixed-criticality real-time ethernet

High-performance imaging subsystems and their integration in mobile devices

Multi-pumping for resource reduction in FPGA high-level synthesis

FaulTM: error detection and recovery using hardware transactional memory

A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model

Capturing post-silicon variation by layout-aware path-delay testing

An efficient network on-chip architecture based on isolating local and non-local communications

Exploiting subarrays inside a bank to improve phase change memory performance

ClockPUF: physical unclonable functions based on clock networks

Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step

Performance analysis of HPC applications on low-power embedded platforms

DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters

Fast and accurate BER estimation methodology for I/O links based on extreme value theory

An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture

Electrical calibration of spring-mass MEMS capacitive accelerometers

Automatic and efficient heap data management for limited local memory multicore architectures

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs

Multi-level phase analysis for sampling simulation

Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors

Towards adaptive test of multi-core RF SoCs

Formal analysis of sporadic bursts in real-time systems

Fast cone-of-influence computation and estimation in problems with multiple properties

The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocks

SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors

A methodology for embedded classification of heartbeats using random projections

Improving fault tolerance utilizing hardware-software-co-synthesis

Efficient and scalable OpenMP-based system-level design

Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits

An area-efficient network interface for a TDM-based network-on-chip

A near-future prediction method for low power consumption on a many-core processor

On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes

Event density analysis for event triggered control systems

Tuning dynamic data flow analysis to support design understanding

A power-driven thermal sensor placement algorithm for dynamic thermal management

Cache coherence enabled adaptive refresh for volatile STT-RAM

Reverse engineering digital circuits using functional analysis

Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches

FBLT: a real-time contention manager with improved schedulability

Explicit transient thermal simulation of liquid-cooled 3D ICs

Optimization techniques for craig interpolant compaction in unbounded model checking

Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories

AVF-driven parity optimization for MBU protection of in-core memory arrays

Pipelets: self-organizing software pipelines for many-core architectures

Cyborg insects, neural interfaces and other things: building interfaces between the synthetic and the multicellular

High-level modeling and synthesis for embedded FPGAs

Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy

Hybrid prototyping of multicore embedded systems

Thermal-aware datapath merging for coarse-grained reconfigurable processors

Crosstalk avoidance codes for 3D VLSI

Effective power network prototyping via statistical-based clustering and sequential linear programming

Smart, connected and mobile: architecting future electric mobility ecosystems

On reconfigurable single-electron transistor arrays synthesis using reordering techniques

PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design

CATALYST: planning layer directives for effective design closure

An automated parallel simulation flow for heterogeneous embedded systems

Runtime power estimation of mobile AMOLED displays

A dual grain hit-miss detector for large die-stacked DRAM caches

A 100 GOPS ASP based baseband processor for wireless communication

Resource-constrained high-level datapath optimization in ASIP design

Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime

Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor

Adaptive reduction of the frequency search space for multi-vdd digital circuits

SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model

Future of GPGPU micro-architectural parameters

Memristor PUFs: a new generation of memory-based physically unclonable functions

Automated determination of top level control signals

Software enabled wear-leveling for hybrid PCM main memory on embedded systems

Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems

Exploring resource mapping policies for dynamic clustering on NoC-based MPSoCs

Reliability analysis for integrated circuit amplifiers used in neural measurement systems

Using cubes of non-state variables with property directed reachability

DANCE: distributed application-aware node configuration engine in shared reconfigurable sensor networks

The design of sustainable wireless sensor network node using solar energy and phase change memory

A survey of multi-source energy harvesting systems

A dynamic self-adaptive correction method for error resilient application

Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications

Optimizing BDDs for time-series dataset manipulation

CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems

Time- and angle-triggered real-time kernel

A fast and Effective DFT for test and diagnosis of power switches in SoCs

Model predictive control over delay-based differentiated services control networks

Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories

Is TSV-based 3D integration suitable for inter-die memory repair?

A practical testing framework for isolating hardware timing channels

A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot

Mitigating dark-silicon problems using superlattice-based thermoelectric coolers

Formal analysis of steady state errors in feedback control systems using HOL-light

Statistical modeling with the virtual source MOSFET model

An enhanced double-TSV scheme for defect tolerance in 3D-IC

An integrated approach for managing the lifetime of flash-based SSDs

Scheduling independent liveness analysis for register binding in high level synthesis

Modeling and analysis of fault-tolerant distributed memories for networks-on-chip

Large-scale flip-chip power grid reduction with geometric templates

A network-flow based algorithm for power density mitigation at post-placement stage

e-Mobility the next frontier for automotive industry

Mutation analysis with coverage discounting

Reducing writes in phase-change memory environments by using efficient cache replacement policies

Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder

User-aware energy efficient streaming strategy for smartphone based video playback applications

Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms

Wireless sensor network simulation for security and performance analysis

Probabilistic timing analysis on conventional cache designs

Characterizing the performance benefits of fused CPU/GPU systems using FusionSim

On-line testing of permanent radiation effects in reconfigurable systems

Bridging the gap between dual propagation and CNF-based QBF solving

Hybrid interconnect design for heterogeneous hardware accelerators

Optical look up table

Capital cost-aware design and partial shading-aware architecture optimization of a reconfigurable photovoltaic system

Incorporating the impacts of workload-dependent runtime variations into timing analysis

An extremely compact JPEG encoder for adaptive embedded systems

Multirate controller design for resource- and schedule-constrained automotive ECUs

Determining relevant model elements for the verification of UML/OCL specifications

Adaptive thermal management for portable system batteries by forced convection cooling

Thermomechanical stress-aware management for 3D IC designs

Sufficient real-time analysis for an engine control unit with constant angular velocities

Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems

A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms

Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects

Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification

Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs

An efficient wirelength model for analytical placement

Semiconductor technologies for smart mobility management

Scalable fault localization for SystemC TLM designs

Utility-aware deferred load balancing in the cloud driven by dynamic pricing of electricity

Using synchronization stalls in power-aware accelerators

An approach for redundancy in FlexRay networks using FPGA partial reconfiguration

A verilog-a model for reconfigurable logic gates based on graphene pn-junctions

An ultra-low power hardware accelerator architecture for wearable computers using dynamic time warping

Design of an ultra-low power device for aircraft structural health monitoring

Towards a generic verification methodology for system models

Exploiting replicated checkpoints for soft error detection and correction

Compiling control-intensive loops for CGRAs with state-based full predication

Leakage and temperature aware server control for improving energy efficiency in data centers

Efficient cache architectures for reliable hybrid voltage operation using EDC codes

SlackProbe: a low overhead in situ on-line timing slack monitoring methodology

Content Provider	ACM Digital Library
Author	Chandra, Vikas Gupta, Puneet Lai, Liangzhen Aitken, Robert
Abstract	In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually incurs significant overhead. We observe that most existing slack monitoring methods exclusively focus on monitoring path ending registers, which is not cost efficient from power and area perspectives. In this paper, we propose SlackProbe methodology, which inserts timing slack monitors like "probes" at a selected set of nets, including intermediate nets along critical paths. SlackProbe can significantly reduce the total number of monitors required at the cost of some additional delay margin. It can be used to detect impending delay failures due to various reasons (process variations, ambient fluctuations, circuit aging, etc.) and can be used with various preventive actions (e.g. voltage/frequency scaling, clock stretching/time borrowing, etc.). Though we focus on monitor selection in this work, we give an example of using SlackProbe with adaptive voltage scaling. Experimental results on commercial processors show that with 5% more timing margin, SlackProbe can reduce the number of monitors by 15-18X as compared to the number of monitors inserted at path ending pins.
Starting Page	282
Ending Page	287
Page Count	6
File Format	PDF
ISBN	9781450321532
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-03-18
Publisher Place	San Jose
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in