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  1. Proceedings of the 9th workshop on MEmory performance (MEDEA '08)
  2. WormBench: a configurable workload for evaluating transactional memory systems
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PFetch: software prefetching exploiting temporal predictability of memory access streams
Modeling of cache access behavior based on Zipf's law
Zero loads: canceling load requests by tracking zero values
A shared cache for a chip multi vector processor
A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches
Predictable dynamic instruction scratchpad for simultaneous multithreaded processors
Exploiting multithreaded architectures to improve the hash join operation
Accurate system-level performance modeling and workload characterization for mobile internet devices
WormBench: a configurable workload for evaluating transactional memory systems
Version management alternatives for hardware transactional memory
Evaluation of memory performance on the cell BE with the SARC programming model

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WormBench: a configurable workload for evaluating transactional memory systems

Content Provider ACM Digital Library
Author Ayguade, Eduard Harris, Tim Unsal, Osman Zyulkyarov, Ferad Cristal, Adrian Cvijic, Sanja Valero, Mateo
Abstract Transactional Memory (TM) is a promising new technology that makes it possible to ease writing multi-threaded applications. Many different TM implementations exist, unfortunately most of those TM systems are currently evaluated by using workloads that are (1) tightly coupled to the interface of a particular TM implementation, (2) are small and lack to capture the common concurrency problems that exist in real multi-threaded applications and also (3) fail to evaluate the overall behavior of the Transactional Memory considering the complete software stack. WormBench is parameterized workload designed from the ground up to evaluate TM systems in terms of robustness and performance. Its goal is to provide an unified solution to the problems stated above (1, 2, 3). The critical sections in the code are marked with the atomic statements and thus proving a framework to test the compiler's ability to translate them properly and efficiently into the appropriate TM system interface. Its design considers the common synchronization problems that exist in TM multi-threaded applications. The behavior of WormBench can be changed by using run configurations which provide the ability to reproduce a runtime behavior observed in a typical multi-threaded application or a behavior that stresses a particular aspect of the TM system such as abort handling. In this paper, we analyze the transactional characteristics of WormBench by studying different run configurations and demonstrate how Worm-Bench can be configured to model the transactional behavior of an application from the STAMP benchmark suite.
Starting Page 61
Ending Page 68
Page Count 8
File Format PDF
ISBN 9781605582436
DOI 10.1145/1509084.1509093
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2008-10-26
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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