NDLI: Predictable dynamic instruction scratchpad for simultaneous multithreaded processors

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Content Provider	ACM Digital Library
Author	Uhrig, Sascha Mische, Jörg Ungerer, Theo Metzlaff, Stefan
Abstract	For precise timing analysis of hard-real applications a predictable memory system is of particular importance. Caches have a great impact on performance, but at the cost of reduced timing predictability. Conventional scratchpads, i.e. statically managed on-chip memories, provide predictable memory accesses, but they are usually badly utilized. Better memory utilization is allowed by dynamically managed scratchpads that are designed for predictability. In this paper we propose a function scratchpad that is dynamically managed in hardware and provides a predictable timing behavior. The function scratchpad exploits a simultaneous multithreaded architecture to increase the pipeline and memory bandwidth utilization while preserving predictability.
Starting Page	38
Ending Page	45
Page Count	8
File Format	PDF
ISBN	9781605582436
DOI	10.1145/1509084.1509090
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-10-26
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Predictable dynamic instruction scratchpad for simultaneous multithreaded processors