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  1. Proceedings of the 9th workshop on MEmory performance (MEDEA '08)
  2. Zero loads: canceling load requests by tracking zero values
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PFetch: software prefetching exploiting temporal predictability of memory access streams
Modeling of cache access behavior based on Zipf's law
Zero loads: canceling load requests by tracking zero values
A shared cache for a chip multi vector processor
A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches
Predictable dynamic instruction scratchpad for simultaneous multithreaded processors
Exploiting multithreaded architectures to improve the hash join operation
Accurate system-level performance modeling and workload characterization for mobile internet devices
WormBench: a configurable workload for evaluating transactional memory systems
Version management alternatives for hardware transactional memory
Evaluation of memory performance on the cell BE with the SARC programming model

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Zero loads: canceling load requests by tracking zero values

Content Provider ACM Digital Library
Author Islam, Mafijul Md. Stenstrom, Per
Abstract The considerable gap between processor and DRAM speed and the power losses in the cache hierarchy calls for more efficient approaches. Broadly speaking, cache-hierarchy efficiency can be increased either by improving cache management or by reducing the number of load instructions that reach the cache hierarchy. We introduce the notion of zero loads to approach the latter. This paper explores the potential of tracking locations that contain the value 'zero'. Loads directed to such locations -- termed Zero Loads -- can be cancelled before they are issued in the cache hierarchy. We find that as many as 21% of the loads are Zero Loads and about one third of them are critical, i.e., ends up on the critical memory path for out-of-order cores. Motivated by this observation, we explore two innovative structures to capture Zero Loads by essentially book-keeping earlier visited blocks/locations that return 'zero'. These schemes are shown to be capable of improving performance and power/energy efficiency considerably.
Starting Page 16
Ending Page 23
Page Count 8
File Format PDF
ISBN 9781605582436
DOI 10.1145/1509084.1509087
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2008-10-26
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Value locality Load criticality Zero load Prediction Cache
Content Type Text
Resource Type Article
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