NDLI: DMATiler: revisiting loop tiling for direct memory access

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DMATiler: revisiting loop tiling for direct memory access

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DMATiler: revisiting loop tiling for direct memory access

Content Provider	ACM Digital Library
Author	Shao, Ling O'Brien, John Kevin Li, Huoding Renganarayana, Lakshminarayanan Chen, Tong Lin, Haibo Liu, Tao
Abstract	In this paper we present the design and implementation of a DMATiler which combines compiler analysis and runtime management to optimize local memory performance. In traditional cache model based loop tiling optimizations, the compiler approximates runtime cache misses as the number of distinct cache lines touched by a loop nest. In contrast, the DMATiler has the full control of the addresses, sizes, and sequences of data transfers. DMATiler uses a simplified DMA performance model to formulate the cost model for DMA-tiled loop nests, then solves it using a custom gradient descent algorithm with heuristics guided by DMA characteristics. Given a loop nest, DMATiler uses loop interchange to make the loop order more friendlier for data movements. Moreover, DMATiler applies compressed data buffer and advanced DMA command to further optimize data transfers. We have implemented the DMATiler in the IBM XL C/C++ for Multi-core Acceleration for Linux, and have conducted experiments with a set of loop nest benchmarks. The results show DMATiler is much more efficient than software controlled cache (average speedup of 9.8x) and single level loop blocking (average speedup of 6.2x) on the Cell BE processor.
Starting Page	559
Ending Page	560
Page Count	2
File Format	PDF
ISBN	9781450301787
DOI	10.1145/1854273.1854351
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-09-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Local memory Loop tiling Multi-core system
Content Type	Text
Resource Type	Article

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