NDLI: Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems

Please wait, while we are loading the content...

Build Watson: an overview of DeepQA for the Jeopardy! challenge

Towards a science of parallel programming

Raising the level of many-core programming with compiler technology: meeting a grand challenge

Power and thermal characterization of POWER6 system

Accelerating multicore reuse distance analysis with sampling and parallelization

WAYPOINT: scaling coherence to thousand-core architectures

Feedback-directed pipeline parallelism

An OpenCL framework for heterogeneous multicores with local memory

On mitigating memory bandwidth contention through bandwidth-aware scheduling

Discovering and understanding performance bottlenecks in transactional applications

Design and implementation of the PLUG architecture for programmable and efficient network lookups

Semi-automatic extraction and exploitation of hierarchical pipeline parallelism using profiling information

Speculative-aware execution: a simple and efficient technique for utilizing multi-cores to improve single-thread performance

SWEL: hardware cache coherence protocols to map shared data onto shared caches

Compiler-assisted data distribution for chip multiprocessors

On-chip network design considerations for compute accelerators

System-level max power (SYMPO): a systematic approach for escalating system-level power consumption using synthetic benchmarks

Simple and fast biased locks

Subspace snooping: filtering snoops with operating system support

Scalable hardware support for conditional parallelization

Twin peaks: a software platform for heterogeneous computing on general-purpose and graphics processors

AKULA: a toolset for experimenting and developing thread placement algorithms on multicore systems

Efficient sequential consistency using conditional fences

A model for fusion and code motion in an automatic parallelizing compiler

The Paralax infrastructure: automatic parallelization with a helping hand

The potential of using dynamic information flow analysis in data value prediction

ATAC: a 1000-core cache-coherent processor with on-chip optical network

Data layout transformation exploiting memory-level parallelism in structured grid many-core applications

Believe it or not!: mult-core CPUs can match GPU performance for a FLOP-intensive application!

Scalable thread scheduling and global power management for heterogeneous many-core architectures

Avoiding deadlock avoidance

Proximity coherence for chip multiprocessors

Reducing task creation and termination overhead in explicitly parallel programs

MapCG: writing parallel program portable between CPU and GPU

Criticality-driven superscalar design space exploration

Partitioning streaming parallelism for multi-cores: a machine learning based approach

Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems

AM++: a generalized active message framework

Efficient runahead threads

Using dead blocks as a virtual victim cache

Tiled-MapReduce: optimizing resource usages of data-parallel applications on multicore with tiling

Ordered and unordered algorithms for parallel breadth first search

Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors

DAFT: decoupled acyclic fault tolerance

SPACE: sharing pattern-based directory coherence for multicore scalability

MEDICS: ultra-portable processing for medical image reconstruction

Adaptive spatiotemporal node selection in dynamic networks

A programmable parallel accelerator for learning and classification

Handling the problems and opportunities posed by multiple on-chip memory controllers

An empirical characterization of stream programs and its implications for language and compiler design

Using memory mapping to support cactus stacks in work-stealing runtime systems

Energy efficient speculative threads: dynamic thread allocation in Same-ISA heterogeneous multicore systems

Moths: mobile threads for on-chip networks

Improving speculative loop parallelization via selective squash and speculation reuse

Revisiting sorting for GPGPU stream architectures

Analyzing cache performance bottlenecks of STM applications and addressing them with compiler's help

An intra-tile cache set balancing scheme

StatCC: a statistical cache contention model

An integer programming framework for optimizing shared memory use on GPUs

Exploiting subtrace-level parallelism in clustered processors

A case for NUMA-aware contention management on multicore systems

DMATiler: revisiting loop tiling for direct memory access

Scaling of the PARSEC benchmark inputs

Online cache modeling for commodity multicore processors

NoC-aware cache design for chip multiprocessors

A software-SVM-based transactional memory for multicore accelerator architectures with local memory

NUcache: a multicore cache organization based on next-use distance

CoreGenesis: erasing core boundaries for robust and configurable performance

Automatic vector instruction selection for dynamic compilation

Approximating age-based arbitration in on-chip networks

Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems

Content Provider	ACM Digital Library
Author	Yalamanchili, Sudhakar Diamos, Gregory Frederick Clark, Nathan Kerr, Andrew Robert
Abstract	Ocelot is a dynamic compilation framework designed to map the explicitly data parallel execution model used by NVIDIA CUDA applications onto diverse multithreaded platforms. Ocelot includes a dynamic binary translator from Parallel Thread eXecution ISA (PTX) to many-core processors that leverages the Low Level Virtual Machine (LLVM) code generator to target x86 and other ISAs. The dynamic compiler is able to execute existing CUDA binaries without recompilation from source and supports switching between execution on an NVIDIA GPU and a many-core CPU at runtime. It has been validated against over 130 applications taken from the CUDA SDK, the UIUC Parboil benchmarks [1], the Virginia Rodinia benchmarks [2], the GPU-VSIPL signal and image processing library [3], the Thrust library [4], and several domain specific applications. This paper presents a high level overview of the implementation of the Ocelot dynamic compiler highlighting design decisions and trade-offs, and showcasing their effect on application performance. Several novel code transformations are explored that are applicable only when compiling explicitly parallel applications and traditional dynamic compiler optimizations are revisited for this new class of applications. This study is expected to inform the design of compilation tools for explicitly parallel programming models (such as OpenCL) as well as future CPU and GPU architectures.
Starting Page	353
Ending Page	364
Page Count	12
File Format	PDF
ISBN	9781450301787
DOI	10.1145/1854273.1854318
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-09-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Ocelot Ptx Cuda
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in