NDLI: Improving the accuracy and performance of memory communication through renaming

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The bi-mode branch predictor

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Alternative fetch and issue policies for the trace cache fetch mechanism

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The design and performance of a conflict-avoiding cache

Prediction caches for superscalar processors

A framework for balancing control flow and predication

Evaluation of scheduling techniques on a SPARC-based VLIW testbed

Tuning compiler optimizations for simultaneous multithreading

Exploiting dead value information

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The multicluster architecture: reducing cycle time through partitioning

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Initial results on the performance and cost of vector microprocessors

The filter cache: an energy efficient memory structure

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Improving the accuracy and performance of memory communication through renaming

Microarchitecture support for improving the performance of load target prediction

Streamlining inter-operation memory communication via data dependence prediction

The predictability of data values

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Highly accurate data value prediction using hybrid predictors

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Available paralellism in video applications

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Improving the accuracy and performance of memory communication through renaming

Content Provider	ACM Digital Library
Author	Tyson, Gary S. Austin, Todd M.
Abstract	As processors continue to exploit more instruction-level parallelism, a greater demand is placed on reducing the effects of memory access latency. In this paper, we introduce a novel modification of the processor pipeline called memory renaming. Memory renaming applies register access techniques to load instructions, reducing the effect of delays caused by the need to calculate effective addresses for the load and all preceding stores before the data can be fetched. Memory renaming allows the processor to speculatively fetch values when the producer of the data can be reliably determined without the need for an effective address. This work extends previous studies of data value and dependence speculation. When memory renaming is added to the processor pipeline, renaming can be applied to 30% to 50% of all memory references, translating to an overall improvement in execution time of up to 41%. Furthermore, this improvement is seen across all memory segments-including the heap segment, which has often been difficult to manage efficiently.
Starting Page	218
Ending Page	227
Page Count	10
File Format	PDF
ISBN	0818679778
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1997-12-01
Access Restriction	Subscribed
Subject Keyword	Heap segment Memory segments Address calculation Instruction loading Data dependence speculation Memory access latency Memory references Stores Processor pipeline Storage allocation Memory communication Instruction-level parallelism Accuracy Register access techniques Data value speculation Delays Memory renaming Performance Data fetching Execution time
Content Type	Text
Resource Type	Article

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