NDLI: Resource-sensitive profile-directed data flow analysis for code optimization

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Foreword

Conference Committee

Program Committee

Reviewers

Speaker Biographies

The bi-mode branch predictor

Path-based next trace prediction

Alternative fetch and issue policies for the trace cache fetch mechanism

Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order

On high-bandwidth data cache design for multi-issue processors

Run-time spatial locality detection and optimization

A comparison of data prefetching on an access decoupled and superscalar machine

The design and performance of a conflict-avoiding cache

Prediction caches for superscalar processors

A framework for balancing control flow and predication

Evaluation of scheduling techniques on a SPARC-based VLIW testbed

Tuning compiler optimizations for simultaneous multithreading

Exploiting dead value information

Trace processors

The multicluster architecture: reducing cycle time through partitioning

Out-of-order vector architectures

Initial results on the performance and cost of vector microprocessors

The filter cache: an energy efficient memory structure

Improving code density using compression techniques

Procedure based program compression

Improving the accuracy and performance of memory communication through renaming

Microarchitecture support for improving the performance of load target prediction

Streamlining inter-operation memory communication via data dependence prediction

The predictability of data values

Value profiling

Can program profiling support value prediction?

Highly accurate data value prediction using hybrid predictors

ProfileMe: hardware support for instruction-level profiling on out-of-order processors

Procedure placement using temporal ordering information

Predicting data cache misses in non-numeric applications through correlation profiling

Available paralellism in video applications

MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems

Cache sensitive modulo scheduling

Unroll-and-jam using uniformly generated sets

Resource-sensitive profile-directed data flow analysis for code optimization

Author Index

Resource-sensitive profile-directed data flow analysis for code optimization

Content Provider	ACM Digital Library
Author	Fang, Jesse Z. Gupta, Rajiv Berson, David A.
Abstract	Instruction schedulers employ code motion as a means of instruction reordering to enable scheduling of instructions at points where the resources required for their execution are available. In addition, driven by the profiling data, schedulers take advantage of predication and speculation for aggressive code motion across conditional branches. Optimization algorithms for partial dead code elimination (PDE) and partial redundancy elimination (PRE) employ code sinking and hoisting to enable optimization. However, unlike instruction scheduling, these optimization algorithms are unaware of resource availability and are incapable of exploiting profiling information, speculation, and predication. In this paper we develop data flow algorithms for performing the above optimizations with the following characteristics: (i) opportunities for PRE and PDE enabled by hoisting and sinking are exploited; (ii) hoisting and sinking of a code statement is driven by availability of functional unit resources; (iii) predication and speculation is incorporated to allow aggressive hoisting and sinking; and (iv) path profile information guides predication and speculation to enable optimization.
Starting Page	358
Ending Page	368
Page Count	11
File Format	PDF
ISBN	0818679778
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1997-12-01
Access Restriction	Subscribed
Subject Keyword	Code optimization Instruction reordering Resource-sensitive profile-directed data flow analysis Resource availability Aggressive code motion Partial dead code elimination Instruction schedulers Data flow analysis Partial redundancy elimination Data flow algorithms Functional unit resources Optimization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Resource-sensitive profile-directed data flow analysis for code optimization (1997).

Partial dead code elimination

Code Optimization as a Side Effect of Instruction Scheduling (1997)

Code Optimization as a Side Effect of Instruction Scheduling (1997)

Abstract partial dead code elimination.

Partial dead code elimination

Partial Dead Code Elimination (1994)

Resource-sensitive profile-directed data flow analysis for code optimization

A Code Motion Framework for Global Instruction Scheduling (1998)

Resource-sensitive profile-directed data flow analysis for code optimization

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