NDLI: Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order

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Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order

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Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order

Content Provider	ACM Digital Library
Author	Stark, Jared Racunas, Paul Patt, Yale N.
Abstract	In conventional processors, each instruction cache fetch brings in a group of instructions. Upon encountering an instruction cache miss, the processor will wait until the instruction cache miss is serviced before continuing to fetch any new instructions. This paper presents a new technique, called out-of-order issue, which allows the processor to temporarily ignore the instructions associated with the instruction cache miss. The processor attempts to fetch the instructions that follow the group of instructions associated with the miss. These instructions are then decoded and written into the processor's reservation stations. Later, after the instruction cache miss has been serviced, the instructions associated with the miss are decoded and written into the reservation stations. (We use the term issue to indicate the act of writing instructions into the reservation stations. With this technique, instructions are not written into the reservation stations in program order. Hence, the term out-of-order issue.) In this paper, we introduce the concept of out-of-order issue, describe its implementation, and present some initial data showing the performance gains possible with out-of-order issue.
Starting Page	34
Ending Page	43
Page Count	10
File Format	PDF
ISBN	0818679778
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1997-12-01
Access Restriction	Subscribed
Subject Keyword	Superscalar processors out-of-order execution instruction supply
Content Type	Text
Resource Type	Article

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