NDLI: CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques

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CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques

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CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques

Content Provider	ACM Digital Library
Author	Li, Sheng Brockman, Jay B. Ahn, Jung Ho Jouppi, Norman P. Chen, Ke
Abstract	This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for implementation overheads, CACTI-P enables in-depth study of architecture-level tradeoffs for advanced leakage power management schemes. We illustrate the potential applicability of CACTI-P in the design and analysis of leakage power reduction techniques of future manycore processors by applying nanosecond scale power-gating to different levels of cache for a 64 core multithreaded architecture at the 22nm technology. Combining results from CACTI-P and a performance simulator, we find that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanosecond scale power-gating a better fit for caches closer to main memory.
Starting Page	694
Ending Page	701
Page Count	8
File Format	PDF
ISBN	9781457713989
ISSN	10923152
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-11-07
Access Restriction	Subscribed
Subject Keyword	Leakage power management Circuit modeling Manycore processor Sram Cache Power-gating
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software Computer Science Applications

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