NDLI: Failure diagnosis of asymmetric aging under NBTI

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Failure diagnosis of asymmetric aging under NBTI

Content Provider	ACM Digital Library
Author	Cao, Yu Velamala, Jyothi Bhaskarr Ravi, Venkatesa
Abstract	Design for reliability is becoming an important step in the design cycle with CMOS technology scaling, demanding need for efficient and accurate reliability simulation methods in the design stage. Traditional aging analysis does not differentiate NBTI induced delay shift in rising and falling edges, thereby assuming averaging effect due to recovery. It is essential to identify the critical operation conditions that are more susceptible to timing violations under aging. In this paper, by identifying the critical moments in circuit operation and considering the asymmetric aging effects, timing violations under NBTI effect are correctly predicted. The unique features of this work include: (1) delay modeling of a digital gate due to threshold voltage $(V_{th})$ shift using delay dependence on supply voltage from cell library; (2) asymmetric aging analysis is conducted by recognizing the critical points in circuit operation; and (3) setup and hold timing violations due to NBTI induced path delay shift in logic and clock buffer are investigated. This failure assessment method is further demonstrated in ISCAS89 benchmark circuits using 45nm Nangate standard cell library to extract aging information in critical paths. The proposed failure diagnosis enables resilient design techniques to mitigate circuit aging under NBTI.
Starting Page	428
Ending Page	433
Page Count	6
File Format	PDF
ISBN	9781457713989
ISSN	10923152
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-11-07
Access Restriction	Subscribed
Subject Keyword	Negative bias temperature instability Design for reliability Static timing analysis Asymmetric aging
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software Computer Science Applications

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