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| Content Provider | ACM Digital Library |
|---|---|
| Author | Vendramini, Julio Goldner Ferreira, Ricardo Pereira, Monica Magalhaes Carro, Luigi Mucida, Lucas |
| Abstract | Coarse-grained reconfigurable architecture has emerged as a promising model for embedded systems as a solution to reduce the complexity of FPGA synthesis and mapping steps, consequently reducing reconfiguration time. Despite these advantages, CGRA usage has been limited due to the lack of commercial CGRA circuits. This work proposes a virtual and dynamic CGRA implemented on top of an FPGA. This approach allows the usage of commercial-off-the-shelf FPGA devices combined with the advantages of CGRAs. The proposed architecture consists of a set of heterogeneous functional units (FU) and a global interconnection network. The global network allows any FU to be used at each cycle, which reduces significantly the placement complexity. In addition, we introduce a polynomial mapping algorithm which includes scheduling, placement and routing steps (SPR). Moreover, the proposed approach performs a very fast placement and routing in comparison to similar CGRA approaches. The three SPR steps are computed in few milliseconds. The feasibility of this approach is demonstrated for a suite of digital signal processing benchmarks. |
| Starting Page | 195 |
| Ending Page | 204 |
| Page Count | 10 |
| File Format | |
| ISBN | 9781450307130 |
| DOI | 10.1145/2038698.2038728 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2011-10-09 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Multistage Cgra Fpga Placement Routing Scheduling Reconfigurable architectures Interconnections |
| Content Type | Text |
| Resource Type | Article |
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