NDLI: Smart cache cleaning: energy efficient vulnerability reduction in embedded processors

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Smart cache cleaning: energy efficient vulnerability reduction in embedded processors

Content Provider	ACM Digital Library
Author	Shrivastava, Aviral Jeyapaul, Reiley
Abstract	Incessant and rapid technology scaling has brought us to a point where todays, and future transistors are susceptible to transient errors induced by energy carrying particles, called soft errors. Within a processor, the sheer size and nature of data in the caches render it most vulnerable to electrical interferences on static data in the cache. Data in the cache is vulnerable to corruption by soft errors, for the time it remains in the cache. Write-through and early-write-back [17] cache configurations reduce the time for vulnerable data in the cache, at the cost of increased memory writes and therefore energy. We propose a smart cache cleaning methodology, that enables copying of only specific vulnerable cache blocks into the memory at chosen times, thereby ensuring data cache protection with minimal memory writes. Our experiments over LINPACK and Livermore benchmarks demonstrate 26% reduced energy-vulnerability product compared to that of hardware cache configurations.
Starting Page	105
Ending Page	114
Page Count	10
File Format	PDF
ISBN	9781450307130
DOI	10.1145/2038698.2038716
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-10-09
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Smart cache architecture Soft error Hybrid technique Cache write-back Vulnerability Energy efficient
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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