NDLI: Variation-aware placement for FPGAs with multi-cycle statistical timing analysis

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Variation-aware placement for FPGAs with multi-cycle statistical timing analysis

Content Provider	ACM Digital Library
Author	Dong, Chen Chen, Deming Lucas, Gregory
Abstract	Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process variation. In order to obtain sufficient yield values, it is now necessary to consider process variation during physical design. It is common for FPGAs to contain designs with multi-cycle paths to help increase the performance, but current SSTA techniques cannot support this type of timing constraint. We propose an extension to block-based SSTA to consider multi-cycle paths. We then use this new SSTA to optimize FPGA placement with our tool VMC-Place for designs with multi-cycle paths. Our experimental results show our multi-cycle SSTA is accurate to 0.59% for the mean and 0.0024% for the standard deviation. Our results also show that VMC-Place is able to improve the clock period by 9.42% or the performance yield by 68.51% compared to a single-cycle variation-aware placer.
Starting Page	177
Ending Page	180
Page Count	4
File Format	PDF
ISBN	9781605589114
DOI	10.1145/1723112.1723143
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-02-21
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Statistical static timing analysis Fpga Placement Multi-cycle Variation-aware Ssta
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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