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| Content Provider | ACM Digital Library |
|---|---|
| Author | Vahid, Frank Huang, Chen |
| Abstract | FPGAs are increasingly used to implement coprocessors for applications running on desktop platforms, and soon such FPGA coprocessing may appear in mobile devices. Because one device may run different applications from another device, different coprocessor sets are needed for each device based on the device's usage. We introduce an approach wherein a device profiles application usage and uploads that information to a server when docked. The server then determines the best coprocessor set based on such usage and on the device's particular FPGA constraints. The server creates the coprocessor set by combining pre-synthesized coprocessors for each application, and considers multiple versions of the same coprocessor, versions that tradeoff speed and size. We introduce a coprocessor set selection problem and propose a Pareto-optimal merge heuristic for the server that yields near-optimal solutions with linear time complexity. We also use a method that avoids time-consuming resynthesis of the coprocessors into a single FPGA binary, by using small reconfigurable regions with reserved inter-region communication channels. Our experiments show that the Pareto-optimal merge heuristic generates results within 1% of the optimal on average and run 5-20x faster than simulated annealing. The experiments also show that a 3x speedup and 70% energy reduction can be achieved by using FPGA coprocessors versus running the applications only on a microprocessor. |
| Starting Page | 125 |
| Ending Page | 134 |
| Page Count | 10 |
| File Format | |
| ISBN | 9781605589114 |
| DOI | 10.1145/1723112.1723135 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2010-02-21 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Fpgas Dynamic optimization Acceleration Coprocessing |
| Content Type | Text |
| Resource Type | Article |
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