NDLI: Frequency and yield optimization using power gates in power-constrained designs

Please wait, while we are loading the content...

Advances in process technology & IBM collaborative ecosystem for leadership power performance SOC designs

Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic

Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction

A low power high noise immunity boost DC-DC converter using the differential difference amplifiers

PPT: joint performance/power/thermal management of DRAM memory for multi-core systems

A 2.6 μW sub-threshold mixed-signal ECG SoC

Frequency and yield optimization using power gates in power-constrained designs

Minimizing data center cooling and server power costs

Circuit design in nano-scale CMOS era: opportunities & challenges

Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy

Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors

Pulse width modulation for reduced peak power full-swing on-chip interconnect

vGreen: a system for energy efficient computing in virtualized environments

Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era

Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking

It is all about power analysis, exploration and trade-offs

Challenges and opportunities in low-power design enablement

Dealing with disaggregation in ever-changing world of semiconductors

A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management

Adaptive RF chain management for energy-efficient spatial-multiplexing MIMO transmission

Ultra low voltage CMOS

Emerging technologies and their impact on system design

Green transistors to green architectures

Green at the micro-scale: towards self-powered embedded systems

Software-defined SIMO step-up/down power converter with adaptive global/local power allocation scheme for DVS-enabled multicore systems

Design and analysis of ultra-thin-body SOI based subthreshold SRAM

Variation-aware supply voltage assignment for minimizing circuit degradation and leakage

A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications

Predict and act: dynamic thermal management for multi-core processors

A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM

NBTI-aware power gating for concurrent leakage and aging optimization

Thinking outside the box: power management at the system level & beyond

Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches

Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator

Low power circuit design based on heterojunction tunneling transistors (HETTs)

Near optimal battery-aware energy management

Non volatile memories to enable system power scaling

Reducing the leakage and timing variability of 2D ICs using 3D ICs

The design of a bloom filter hardware accelerator for ultra low power systems

Remote progressive firmware update for flash-based networked embedded systems

Slew-aware clock tree design for reliable subthreshold circuits

A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation

A CMOS low power current-mode polyphase filter

Online work maximization under a peak temperature constraint

The opportunity cost of low power design: a case study in circuit tuning

A look inside IBM's green data center research

Energy-efficient renaming with register versioning

Optimizing total power of many-core processors considering voltage scaling limit and process variations

A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications

Transaction-based adaptive dynamic voltage scaling for interactive applications

Low voltage tunnel transistor architecture and its viability for energy efficient logic applications

An optimization strategy for low energy and high performance for the on-chip interconnect signalling

Dynamic power gating with quality guarantees

Power management in energy harvesting embedded systems with discrete service levels

Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits

Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits

Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination

Dynamic thermal management using thin-film thermoelectric cooling

Behavior-level observability don't-cares and application to low-power behavioral synthesis

Sustainable IT ecosystems and data centers

Cooperative shared resource access control for low-power chip multiprocessors

Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection

A low power 3D integrated FFT engine using hypercube memory division

Tracking the power in an enterprise decision support system

A high-performance low-power nanophotonic on-chip network

End-to-end validation of architectural power models

Energy efficient sampling for event detection in wireless sensor networks

Serial sub-threshold circuits for ultra-low-power systems

Statistical static timing analysis considering leakage variability in power gated designs

Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories

An energy-efficient checkpointing mechanism for out of order commit processor

Data manipulation techniques to reduce phase change memory write energy

Ranking servers based on energy savings for computation offloading

Exploration of 3D stacked L2 cache design for high performance and efficient thermal control

Low power fast and dense longest prefix match content addressable memory for IP routers

Power-management-based Chien search for low power BCH decoder

MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency

Low power robust signal processing

Enabling ultra low voltage system operation by tolerating on-chip cache failures

Design of multi-mode 4-switch buck-boost controller

Electromigration study of power-gated grids

A novel 0.5 V 15 μW 1.3 MHz temperature-compensated analog PWM-controller for switch-mode converters

SOI, interconnect, package, and mainboard thermal characterization

N-version temperature-aware scheduling and binding

Energy-aware instruction-set customization for real-time embedded multiprocessor systems

Power-saving color transformation of mobile graphical user interfaces on OLED-based displays

An energy-delay efficient 2-level data cache architecture for embedded system

Experimental analysis of sequence dependence on energy saving for error tolerant image processing

A programmable implementation of neural signal processing on a smartdust for brain-computer interfaces

An experimental validation of system level design space exploration methodology for energy efficient sensor nodes

Frequency and yield optimization using power gates in power-constrained designs

Content Provider	ACM Digital Library
Author	Lee, Jungseob Kim, Nam Sung Choi, Ken Shin, Youngsoo Sinkar, Abhishek Han, Tae Hee Seomun, Jun
Abstract	Manufactured dies exhibit a large spread of maximum frequency and leakage power due to process variations, which have been increasing with technology scaling. Reducing the spread is very important for maximizing the frequency and the yield of power-constrained designs, because otherwise many dies that do not satisfy frequency or power constraints would be discarded. In this paper, we propose two optimization methods to improve the maximum operating frequency and the yield using power gates that already exist in many power-constrained designs. In the first method, we consider the designs of multiple cores, where each of them can be independently power-gated. When each core shows different frequencies due to within-die variations, the strength of a power gate in each core is adjusted to make their maximum operating frequencies even. This allows faster cores to consume less active leakage power, reducing the total power consumption well below a power constraint in a globally-clocked design. We subsequently increase global supply voltage for higher overall frequency until the power constraint is satisfied. In our experiments assuming multicore processors with 2--16 cores, the maximum operating frequency was improved by 4-23%. In the second method, we take leaky-but-fast dies (which otherwise would be discarded) and adjust the strength of the power gates such that they can operate in an acceptable power and frequency region. The problem is extended to designs employing a frequency binning strategy, where we have an additional objective of maximizing the number of dies for higher frequency bins. In our experiments with ISCAS benchmark circuits, most discarded fast-but leaky dies were recovered using the second method.
Starting Page	121
Ending Page	126
Page Count	6
File Format	PDF
ISBN	9781605586847
DOI	10.1145/1594233.1594263
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-08-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Frequency Power gate Yield Optimization
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in