NDLI: Efficient static timing analysis and applications using edge masks

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Efficient static timing analysis and applications using edge masks

Content Provider	ACM Digital Library
Author	Karchmer, David Govig, Jason Hutton, Mike Archell, Bryan
Abstract	Static timing analysis (STA) with multiple clock domains and complicated exception conditions is a complex practical problem that can dramatically increase compilation time, both for back-end analysis and during place and route. In FPGA placement, timing analysis with many constraints can dominate placement run-time.In this paper we introduce a simple binary edge-mask data structure on arcs in a timing netlist which allows for efficient timing analysis in the presence of many such constraints. The technique applies to either BFS or DFS-based timing analysis. Preliminary implementations on just the basic concept show a 59% decrease in STA run-time for multi-clock designs, indicating that significant benefit is to be gained from a complete implementation. On a set of heavily constrained designs this benefit improved to 80% run-time decrease.Further applications of the edge-mask concept are shown to efficiently deal with thru-x constraints, enumerating the k-longest paths in a timing graph, and partial/incremental timing analysis aimed at significant improvements in placement time.
Starting Page	174
Ending Page	183
Page Count	10
File Format	PDF
ISBN	1595930299
DOI	10.1145/1046192.1046215
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-02-20
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Thru-x Fpga Placement Cut-path Multicycle Timing analysis
Content Type	Text
Resource Type	Article

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