NDLI: Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only)

Content Provider	ACM Digital Library
Author	Pedram, Hossein Saleh, Kamran Naderi, Mohsen Sedighi, Mehdi Najibi, Mehrdad
Abstract	This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19.6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.
Starting Page	269
Ending Page	269
Page Count	1
ISBN	1595930299
DOI	10.1145/1046192.1046243
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-02-20
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only)