NDLI: Combining low-leakage techniques for FPGA routing design

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Combining low-leakage techniques for FPGA routing design

Content Provider	ACM Digital Library
Author	Lodi, Andrea Ciccarelli, Luca Giansante, Roberto
Abstract	Reconfigurable architectures are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to 90nm technology and below, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. We propose to combine super cut-off, body biasing and multi-threshold techniques to reduce the leakage current of programmable interconnections, which give by far the main contribution to static power dissipation. Super cut-off (gate biasing) technique is well suited for high-speed pass-transistors, while body biasing can be adopted for large buffers. On the other hand high threshold transistors can be used where delays are not critical. We show the design of SRAM cells generating the required high swing signals for gate-biased and body-biased transistors without affecting transistor reliability. Compared to a standard design the adoption of a mixed technique reduces routing leakage by more than one order of magnitude with only a 5% increase in switch delay and a 9% in tile area, while with respect to a full dual-threshold approach, delay is reduced by 23%.
Starting Page	208
Ending Page	214
Page Count	7
File Format	PDF
ISBN	1595930299
DOI	10.1145/1046192.1046219
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-02-20
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpga Low leakage Power
Content Type	Text
Resource Type	Article

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