NDLI: Massively parallel processing on a chip

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Massively parallel processing on a chip

Content Provider	ACM Digital Library
Author	Duquennoy, Simon Le Beux, Sébastien Marquet, Philippe Meftali, Samy Dekeyser, Jean-Luc
Abstract	MppSoC is a SIMD architecture composed of a grid of processors andmemories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution of the famous massively parallel systems proposed at the end of the eighties. We claim that today such a machine may be integrated in a single chip. On one side, new design methodologies such as IP reuse and, on the other side, thepossible high level of integration on a chip let us envisage sucha revival. Some improvements of the system architecture are possible because of the high degree of integration: The mppSoC processing elements sharemost of their design with the control processor, the integrated network allows to exchange data between PEs, but also between thecontrol processor and the PE memories, and even to connect the external devices to the system. This paper presents the mppSoC architecture, a cycle-accurate bit-accurate SystemC simulator of this architecture, and a prototype of implementation on FPGA. A complete tool chain and the execution ofsome applications on the simulator and the FPGA implementation validate the modeling choices and show the effectiveness of this design.
Starting Page	277
Ending Page	286
Page Count	10
File Format	PDF
ISBN	9781595936837
DOI	10.1145/1242531.1242571
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-05-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Maspar Massively parallelism Soc Simd System-on-a-chip Mppsoc
Content Type	Text
Resource Type	Article

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