NDLI: Functional verification of power gate design in SystemC RTL

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Functional verification of power gate design in SystemC RTL

Content Provider	ACM Digital Library
Author	Silveira, George Sobral Brito, Alisson Vasconcelos Melcher, Elmar U. K.
Abstract	With the growth of number of transistors, thermal density and market drive towards battery power, the necessity to develop low power integrated circuits is evident. There are several methodologies and techniques that help in the development of this type of SoC. There is consensus that the techniques when applied in the initial phases of the design flow, especially in design and architecture of the system have a higher impact factor in relation to those applied during the implementation or layout phase. Considering this fact, the possibility to accomplish functional verification of the system with low power design modeled in TLM and RTL is attractive. The purpose of this paper is to show a method for functional verification of power gate design in RTL. A case study is presented to demonstrate the application of power gate using new features for the OSCI SystemC simulator developed for this purpose and the accomplishment of the functional verification of the design using the VeriSC methodology.
Starting Page	1
Ending Page	5
Page Count	5
File Format	PDF
ISBN	9781605587059
DOI	10.1145/1601896.1601963
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-08-31
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Simulation Power gate Rtl Systemc Functional verification
Content Type	Text
Resource Type	Article

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