NDLI: A novel scheme to reduce short-circuit power in mesh-based clock architectures

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Sizing CMOS circuits by means of the gm/ID methodology and a compact model

System-level design technologies for heterogeneous distributed systems

Lithography friendly routing: from construct-by-correction to correct-by-construction

Challenges of the nanoscale era

Full-chip routing system for reducing Cu CMP & ECP variation

Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA

A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model

A current limiter for DC/DC regulators with internal compensation for process and temperature

A novel scheme to reduce short-circuit power in mesh-based clock architectures

An improved and automated design tool for the optimization of CMOS OTAs using geometric programming

A simplified executable model to evaluate latency and throughput of networks-on-chip

Fault-tolerance in FPGA's through CRC voting

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV

Synergistic modeling and optimization for nanometer IC design/manufacturing integration

Time-domain analog signal processing techniques

Metal filling impact on standard cells: definition of the metal fill corner concept

The performance of pollution control victim cache for embedded systems

A 40mhz 70db gain variable gain amplifier design using the gm/id design method

Current mode read-out circuit for infrared photodiode applications in 0.35 μm cmos

Power and performance tradeoffs with process variation resilient adaptive cache architectures

CMOS op-amp power optimization in all regions of inversion using geometric programming

Executable formal specification and validation of NoC communication infrastructures

Evaluating the robustness of secure triple track logic through prototyping

A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter

Test Methods For Sigma-Delta Data Converters and Related Devices

System design for 3D Silicon integration

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

Low-area ASIC implementation for configurable coefficients FIR pulse shape filters of digital TV systems

A 2.7ua sub1-v voltage reference

Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors

Power management techniques for very low consumption and EMI reduction in automotive applications

Systematic methodology for the design of Seevinck's CMOS log-domain integrators

MOTIM: an industrial application using nocs

Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications

High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV

Highly integrated, re-configurable RF front-ends in deep sub-micron CMOS: (with an example of a WCDMA, GSM/GPRS/EDGE receiver without inter-stage SAW filter)

A new march sequence to fit DDR SDRAM test in burst mode

An approximate algorithm for the multiple constant multiplications problem

A wide band CMOS differential voltage-controlled ring oscillator

Encountering gate oxide breakdown with shadow transistors to increase reliability

A coloured petri net based approach for estimating execution time and energy consumption in embedded systems

BenCGen: a digital circuit generation tool for benchmarks

Self-adaptable slew rate control output buffer for embedded microcontroller port applications

Analog hardware implementation of a vector quantizer for focal-plane image compression

An efficient test and characterization approach for nanowire-based architectures

Area optimization algorithms in high-speed digital FIR filter synthesis

RBF circuits based on folded cascode differential pairs

A novel AES cryptographic core highly resistant to differential power analysis attacks

Efficient dynamic reconfiguration for multi-context embedded FPGA

A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis

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