NDLI: Modulo schedule buffers

Please wait, while we are loading the content...

Fifty years of microarchitecture

Skipper: a microarchitecture for exploiting control-flow independence

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources

Emerging applications for the connected home

Modulo schedule buffers

Efficient static single assignment form for predication

Select-free instruction scheduling logic

Saving energy with architectural and frequency adaptations for multimedia applications

Speculative lock elision: enabling highly concurrent multithreaded execution

Message from the General Chair

Performance characterization of a hardware mechanism for dynamic optimization

A code decompression architecture for VLIW processors

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

Graph-partitioning based instruction scheduling for clustered processors

The impact of if-conversion and branch prediction on program execution on the Intel® Itanium™ processor

Dual use of superscalar datapath for transient-fault detection and recovery

Enhancing loop buffering of media and telecommunications applications using low-overhead predication

Dynamic speculative precomputation

Message from the Program Chair

Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems

Direct load: dependence-linked dataflow resolution of load address and cache coordinate

Reducing power with dynamic critical path information

Modulo scheduling with integrated register spilling for clustered VLIW architectures

Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T)

A high-speed dynamic instruction scheduling scheme for superscalar processors

Cool-cache for hot multimedia

Handling long-latency loads in a simultaneous multithreading processor

Committees

A design space evaluation of grid processor architectures

Direct addressed caches for reduced power consumption

Reducing the complexity of the register file in dynamic superscalar processors

ZR: a 3D API transparent technology for chunk rendering

Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing

Reviewers

Index of Authors

Modulo schedule buffers

Content Provider	ACM Digital Library
Author	Merten, Matthew C. Hwu, Wen-mei W.
Abstract	As VLIW/EPIC processors are increasingly used in real-time, signal-processing, and embedded applications, the importance of minimizing code size and reducing power is growing. This paper describes a new architectural mechanism, called the Modulo Schedule Buffers, that provides an elegant interface for the execution of modulo scheduled loops. While the performance is similar to that of kernel-only modulo scheduling, this mechanism has a number of advantages, including minimal code expansion. Rather than generating fully-scheduled kernels, the compiler generates a sequential form of the modulo scheduled loop body. Using the sequential form, the hardware internally synthesizes the prologue, kernel, and epilogue. In addition, while loops can be scheduled with fewer constraints and fewer explicit prologues/epilogues than with existing mechanisms. Because the hardware controls loop execution, the burden of modulo schedule loop control is lifted from the predicate register file, allowing for a less rigorous predication implementation. Finally; hardware control limits the interrupt latency when using the EQ explicit latency model to the execution latency of one iteration, rather than the whole loop invocation.
Starting Page	138
Ending Page	149
Page Count	12
File Format	PDF
ISBN	0769513697
ISSN	10724451
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-12-01
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Modulo schedule buffers

Modulo Schedule Buffers (2001)

Minimum register requirements for a modulo schedule

Fast modulo scheduling under the simplex scheduling framework (1995).

Minimum register requirements for a modulo schedule (1994)

An interleaved cache clustered VLIW processor

Minimum Register Requirements for a Modulo Schedule (1994)

Stage scheduling: a technique to reduce the register requirements of a modulo schedule

Abstract The Regular Unwinding Framework

Modulo schedule buffers

Similar Documents

Modulo schedule buffers

Modulo Schedule Buffers (2001)

Minimum register requirements for a modulo schedule

Fast modulo scheduling under the simplex scheduling framework (1995).

Minimum register requirements for a modulo schedule (1994)

An interleaved cache clustered VLIW processor

Minimum Register Requirements for a Modulo Schedule (1994)

Stage scheduling: a technique to reduce the register requirements of a modulo schedule

Abstract The Regular Unwinding Framework

Modulo schedule buffers