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| Content Provider | ACM Digital Library |
|---|---|
| Author | Ogras, Umit Marculescu, Diana Marculescu, Radu Garg, Siddharth |
| Abstract | In this paper, we consider the case of network-on-chip (NoC) based multiple-processor systems-on-chip (MPSoCs) implemented using multiple voltage and frequency islands (VFIs) that rely on fine-grained dynamic voltage and frequency scaling (DVFS) for run-time control of the system power dissipation. Specifically, we present a framework to compute theoretical bounds on the performance of DVFS controllers for such systems under the impact of three important technology driven constraints: (i) reliability and temperature driven upper limits on the maximum supply voltage; (ii) inductive noise driven constraints on the maximum rate of change of voltage/frequency; and (iii) increasing manufacturing process variations. Our experimental results show that, for the benchmarks considered, any DVFS control algorithm will lose up to 87% performance, measured in terms of the number of steps required to reach a reference steady state, in the presence of maximum frequency and maximum frequency increment constraints. In addition, increasing process variations can lead to up to 60% of fabricated chips being unable to meet the specified DVFS control specifications, irrespective of the DVFS algorithm used. |
| Starting Page | 818 |
| Ending Page | 821 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781605584973 |
| DOI | 10.1145/1629911.1630120 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2009-07-26 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Power management Performance bounds Networks-on-chip |
| Content Type | Text |
| Resource Type | Article |
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