NDLI: Statistical multilayer process space coverage for at-speed test

Please wait, while we are loading the content...

System prototypes: virtual, hardware or hybrid?

Circuit techniques for dynamic variation tolerance

Worst-case aggressor-victim alignment with current-source driver models

Way Stealing: cache-assisted automatic instruction set extensions

Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study

Carbon nanotube circuits in the presence of carbon nanotube density variations

EDA in flux: should I stay or should I go?

Design perspectives on 22nm CMOS and beyond

Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability

Non-intrusive dynamic application profiling for multitasked applications

Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence

GPU friendly fast Poisson solver for structured power grid network analysis

Moore's Law: another casualty of the financial meltdown?

Holistic verification: myth or magic bullet?

An efficient approach for system-level timing simulation of compiler-optimized embedded software

Analysis and mitigation of process variation impacts on Power-Attack Tolerance

ILP-based pin-count aware design methodology for microfluidic biochips

Soft connections: addressing the hardware-design modularity problem

DFM: don't care or competitive weapon?

The semiconductor industry's nanoelectronics research initiative: motivation and challenges

An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction

Statistical multilayer process space coverage for at-speed test

Finding deterministic solution from underdetermined equation: large-scale performance modeling by least angle regression

Timing-driven optimization using lookahead logic circuits

Oil fields, hedge funds, and drugs

Human computation

A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion

A novel verification technique to uncover out-of-order DUV behaviors

Accurate temperature estimation using noisy thermal sensors

SRAM parametric failure analysis

Guess, solder, measure, repeat: how do I get my mixed-signal chip right?

The Cilk++ concurrency platform

Provably good and practically efficient algorithms for CMP dummy fill

Event-driven gate-level simulation with GP-GPUs

Spectrum: a hybrid nanophotonic-electric on-chip network

Thermal-driven analog placement considering device matching

Serial reconfigurable mismatch-tolerant clock distribution

Debugging from high level down to gate level

Power modeling of graphical user interfaces on OLED displays

A physical unclonable function defined using power distribution system equivalent resistance variations

On systematic illegal state identification for pseudo-functional testing

WCET-aware register allocation based on graph coloring

From milliwatts to megawatts: system level power challenge

A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction

Throughput optimal task allocation under thermal constraints for multi-core processors

An SDRAM-aware router for Networks-on-Chip

Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems

Dynamic thread and data mapping for NoC based CMPs

The wild west: conquest of complex hardware-dependent software design

Internet-in-a-Box: emulating datacenter network architectures using FPGAs

Optimum LDPC decoder: a memory architecture problem

Reduction techniques for synchronous dataflow graphs

Polynomial datapath optimization using partitioning and compensation heuristics

ARMS - automatic residue-minimization based sampling for multi-point modeling techniques

Enabling adaptability through elastic clocks

A moment-based effective characterization waveform for static timing analysis

SysCOLA: a framework for co-development of automotive software and system platform

Selective wordline voltage boosting for caches to manage yield under process variations

Decoding nanowire arrays fabricated with the multi-spacer patterning technique

Creating an affordable 22nm node using design-lithography co-optimization

A Gaussian mixture model for statistical timing analysis

A trace-capable instruction cache for cost efficient real-time program trace compression in SoC

Resurrecting infeasible clock-gating functions

Fast vectorless power grid verification using an approximate inverse technique

Verification problems in reusing internal design components

MPTLsim: a simulator for X86 multicore processors

Evaluating design trade-offs in customizable processors

O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration

A computing origami: folding streams in FPGAs

Single-electron devices for ubiquitous and secure computing applications

GRIP: scalable 3D global routing using integer programming

Speedpath analysis based on hypothesis pruning and ranking

A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian

Simulation and SAT-based Boolean matching for large Boolean networks

How to make computers that work like the brain

Spare-cell-aware multilevel analytical placement

Shortening the verification cycle with synthesizable abstract models

Spectral techniques for high-resolution thermal characterization with limited sensor data

Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm

Misleading performance claims in parallel computations

Predicting variability in nanoscale lithography processes

Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts

Exploring serial vertical interconnects for 3D ICs

Yield-driven iterative robust circuit optimization algorithm

Thermal-aware data flow analysis

The day Sherlock Holmes decided to do EDA

Energy-aware error control coding for Flash memories

Hardware authentication leveraging performance limits in detailed simulations and emulations

Automated failure population creation for validating integrated circuit diagnosis methods

Optimal static WCET-aware scratchpad allocation of program code

Variational capacitance extraction of on-chip interconnects based on continuous surface model

An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems

Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency

Multicore parallel min-cost flow algorithm for CAD applications

A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems

Sustainable data centers: enabled by supply and demand side management

A DVS-based pipelined reconfigurable instruction memory

A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management

Register allocation for high-level synthesis using dual supply voltages

An efficient passivity test for descriptor systems via canonical projector techniques

Addressing design margins through error-tolerant circuits

A false-path aware formal static timing analyzer considering simultaneous input transitions

Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis

Double patterning lithography friendly detailed routing with redundant via consideration

Boolean logic function synthesis for generalised threshold gate circuits

Device/circuit interactions at 22nm technology node

A stochastic jitter model for analyzing digital timing-recovery circuits

Generating test programs to cover pipeline interactions

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications

Computing bounds for fault tolerance using formal techniques

Exploiting "architecture for verification" to streamline the verification process

Trace-driven workload simulation method for Multiprocessor System-On-Chips

A design flow for application specific heterogeneous pipelined multiprocessor systems

BDD-based synthesis of reversible logic for large functions

Retiming and recycling for elastic systems with early evaluation

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions

Automatic bus planner for dense PCBs

Interconnection fabric design for tracing signals in post-silicon validation

Stochastic steady-state and AC analyses of mixed-signal systems

New spare cell design for IR drop minimization in Engineering Change Order

Handling complexities in modern large-scale mixed-size placement

Non-cycle-accurate sequential equivalence checking

Dynamic thermal management via architectural adaptation

Improving testability and soft-error resilience through retiming

Massively parallel processing: it's déjà vu all over again

Variability analysis under layout pattern-dependent rapid-thermal annealing process

Constraints in one-to-many concretization for abstraction refinement

No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips

Contract-based system-level composition of analog circuits

Nanoscale digital computation through percolation

Debugging strategies for mere mortals

PDRAM: a hybrid PRAM and DRAM main memory system

Hardware Trojan horse detection using gate-level characterization

Fault models for embedded-DRAM macros

A real-time program trace compressor utilizing double move-to-front method

PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation

Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack

Vicis: a reliable network for unreliable silicon

FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation

Quality-driven synthesis of embedded multi-mode control systems

Green data centers and hot chips

LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors

Mode grouping for more effective generalized scheduling of dynamic dataflow applications

GPU-based parallelization for fast circuit optimization

A parameterized mask model for lithography simulation

Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating

Use of lithography simulation for the calibration of equation-based design rule checks

Improving STT MRAM storage density through smaller-than-worst-case transistor sizing

Beyond innovation: dealing with the risks and complexity of processor design in 22nm

Statistical ordering of correlated timing quantities and its application for path ranking

NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core

ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models

Clock skew optimization via wiresizing for timing sign-off covering all process corners

Role of the verification team throughout the ASIC development life cycle

Xquasher: a tool for efficient computation of multiple linear expressions

Speculation in elastic systems

CMOS scaling beyond 32nm: challenges and opportunities

A correct network flow model for escape routing

Online cache state dumping for processor debug

Parallelizable stable explicit numerical integration for efficient circuit simulation

Matching-based minimum-cost spare cell selection for design changes

RegPlace: a high quality open-source placement framework for structured ASICs

Regression verification

On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration

Statistical reliability analysis under process variation and aging effects

A learning digital computer

MAGENTA: transaction-based statistical micro-architectural root-cause analysis

A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors

Process variation characterization of chip-level multiprocessors

Adaptive test elimination for analog/RF circuits

Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators

An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapes

Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization

Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective

FPGA-based accelerator for the verification of leading-edge wireless systems

Context-sensitive timing analysis of Esterel programs

Hierarchical architecture of flash-based storage systems for high performance and durability

Efficient program scheduling for heterogeneous multi-core processors

Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors

A parametric approach for handling local variation effects in timing analysis

Flip-chip routing with unified area-I/O pad assignments for package-board co-design

Efficient design-specific worst-case corner extraction for integrated circuits

Handling don't-care conditions in high-level synthesis and application for reducing initialized registers

Programmable neural processing on a smartdust

Untwist your brain: efficient debugging and diagnosis of complex assertions

Information hiding for trusted system design

NoC topology synthesis for supporting shutdown of voltage islands in SoCs

Transmuting coprocessors: dynamic loading of FPGA coprocessors

Scheduling the FlexRay bus using optimization techniques

Human computing for EDA

Beyond verification: leveraging formal for debugging

Synthesizing hardware from sketches

Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivity

Statistical multilayer process space coverage for at-speed test

Content Provider	ACM Digital Library
Author	Xiong, Jinjun Zolotov, Vladimir Visweswariah, Chandu Shi, Yiyu
Abstract	Increasingly large process variations make selection of a set of critical paths for at-speed testing essential yet challenging. This paper proposes a novel multilayer process space coverage metric to quantitatively gauge the quality of path selection. To overcome the exponential complexity in computing such a metric, this paper reveals its relationship to a concept called order statistics for a set of correlated random variables, efficient computation of which is a hitherto open problem in the literature. This paper then develops an elegant recursive algorithm to compute the order statistics (or the metric) in provable linear time and space. With a novel data structure, the order statistics can also be incrementally updated. By employing a branch-and-bound path selection algorithm with above techniques, this paper shows that selecting an optimal set of paths for a multi-million-gate design can be performed efficiently. Compared to the state-of-the-art, experimental results show both the efficiency of our algorithms and better quality of our path selection.
Starting Page	340
Ending Page	345
Page Count	6
File Format	PDF
ISBN	9781605584973
DOI	10.1145/1629911.1630004
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-07-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Path selection Order statistics Process space coverage
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in