NDLI: Automatic bus planner for dense PCBs

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Automatic bus planner for dense PCBs

Content Provider	ACM Digital Library
Author	Wong, Martin D. F. Yan, Tan Kong, Hui
Abstract	Since no commercial PCB routing tools can solve the routing problem for today's complex PCBs, these circuit boards have to be routed manually, taking about 2 months of time per board. Bus planning is one of the most time-consuming steps of PCB routing. It consists of assigning buses to multiple layers of the PCB and routing them in a planar fashion on each layer. Routing congestion between on-board components and the min-max length bounds of the buses must also be considered during routing. In this paper, we present the first automatic bus planner. We tested our system on a state-of-the-art industrial circuit board with over 7000 nets and 12 signal layers. All the nets on this board were already manually routed. Our bus planner is able to achieve 100% routing completion using the layer assignment extracted from manual design. For simultaneous layer assignment and bus routing, we are able to successfully route 98.5% of the nets. The remaining 1.5% can be routed either manually or by using vias. The runtime of our bus planner is less than 3 hours on a 3 Ghz workstation.
Starting Page	326
Ending Page	331
Page Count	6
File Format	PDF
ISBN	9781605584973
DOI	10.1145/1629911.1630000
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-07-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Bus planning Layer assignment Pcb routing Topological routing
Content Type	Text
Resource Type	Article

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