NDLI: Globally homogeneous, locally adaptive sparse matrix-vector multiplication on the GPU

Please wait, while we are loading the content...

Demystifying automata processing: GPUs, FPGAs or Micron's AP?

Novel HPC techniques to batch execution of many variable size BLAS computations on GPUs

Compile-time optimized and statically scheduled N-D convnet primitives for multi-core and many-core (Xeon Phi) CPUs

Fast segmented sort on GPUs

GraphGrind: addressing load imbalance of graph partitioning

Carpool: a bufferless on-chip network supporting adaptive multicast and hotspot alleviation

Iteration-fusing conjugate gradient

Efficient SIMD and MIMD parallelization of hash-based aggregation by conflict mitigation

Enabling scalability-sensitive speculative parallelization for FSM computations

Packet coalescing exploiting data redundancy in GPGPU architectures

HPAT: high performance analytics with scripting ease-of-use

Globally homogeneous, locally adaptive sparse matrix-vector multiplication on the GPU

Automatic topology mapping of diverse large-scale parallel applications

Way-combining directory: an adaptive and scalable low-cost coherence directory

Supporting automatic recovery in offloaded distributed programming models through MPI-3 techniques

Revisiting phased transactional memory

SPIRIT: a framework for creating distributed recursive tree applications

Dynamic scheduling for efficient hierarchical sparse matrix operations on the GPU

Simplification and runtime resolution of data dependence constraints for loop transformations

On improving performance of sparse matrix-matrix multiplication on GPUs

Design and implementation of bandwidth-aware memory placement and migration policies for heterogeneous memory systems

HiPA: history-based piecewise approximation for functions

Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures

Frequent subtree mining on the automata processor: challenges and opportunities

Optimizing recursive task parallel programs

A performance analysis framework for exploiting GPU microarchitectural capability

SSDUP: a traffic-aware ssd burst buffer for HPC systems

libPRISM: an intelligent adaptation of prefetch and SMT levels

Globally homogeneous, locally adaptive sparse matrix-vector multiplication on the GPU

Content Provider	ACM Digital Library
Author	Steinberger, Markus Zayer, Rhaleb Seidel, Hans-Peter
Abstract	The rising popularity of the graphics processing unit (GPU) across various numerical computing applications triggered a breakneck race to optimize key numerical kernels and in particular, the sparse matrix-vector product (SpMV). Despite great strides, most existing GPU-SpMV approaches trade off one aspect of performance against another. They either require preprocessing, exhibit inconsistent behavior, lead to execution divergence, suffer load imbalance or induce detrimental memory access patterns. In this paper, we present an uncompromising approach for SpMV on the GPU. Our approach requires no separate preprocessing or knowledge of the matrix structure and works directly on the standard compressed sparse rows (CSR) data format. From a global perspective, it exhibits a homogeneous behavior reflected in efficient memory access patterns and steady per-thread workload. From a local perspective, it avoids heterogeneous execution paths by adapting its behavior to the work load at hand, it uses an efficient encoding to keep temporary data requirements for on-chip memory low, and leads to divergence-free execution. We evaluate our approach on more than 2500 matrices comparing to vendor provided, and state-of-the-art SpMV implementations. Our approach not only significantly outperforms approaches directly operating on the CSR format ( 20% average performance increase), but also outperforms approaches that preprocess the matrix even when preprocessing time is discarded. Additionally, the same strategies lead to significant performance increase when adapted for transpose SpMV.
Starting Page	1
Ending Page	11
Page Count	11
File Format	PDF
ISBN	9781450350204
DOI	10.1145/3079079.3079086
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-06-14
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Spmv Linear algebra Sparse matrix Gpu
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in