NDLI: Packet coalescing exploiting data redundancy in GPGPU architectures

Please wait, while we are loading the content...

Demystifying automata processing: GPUs, FPGAs or Micron's AP?

Novel HPC techniques to batch execution of many variable size BLAS computations on GPUs

Compile-time optimized and statically scheduled N-D convnet primitives for multi-core and many-core (Xeon Phi) CPUs

Fast segmented sort on GPUs

GraphGrind: addressing load imbalance of graph partitioning

Carpool: a bufferless on-chip network supporting adaptive multicast and hotspot alleviation

Iteration-fusing conjugate gradient

Efficient SIMD and MIMD parallelization of hash-based aggregation by conflict mitigation

Enabling scalability-sensitive speculative parallelization for FSM computations

Packet coalescing exploiting data redundancy in GPGPU architectures

HPAT: high performance analytics with scripting ease-of-use

Globally homogeneous, locally adaptive sparse matrix-vector multiplication on the GPU

Automatic topology mapping of diverse large-scale parallel applications

Way-combining directory: an adaptive and scalable low-cost coherence directory

Supporting automatic recovery in offloaded distributed programming models through MPI-3 techniques

Revisiting phased transactional memory

SPIRIT: a framework for creating distributed recursive tree applications

Dynamic scheduling for efficient hierarchical sparse matrix operations on the GPU

Simplification and runtime resolution of data dependence constraints for loop transformations

On improving performance of sparse matrix-matrix multiplication on GPUs

Design and implementation of bandwidth-aware memory placement and migration policies for heterogeneous memory systems

HiPA: history-based piecewise approximation for functions

Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures

Frequent subtree mining on the automata processor: challenges and opportunities

Optimizing recursive task parallel programs

A performance analysis framework for exploiting GPU microarchitectural capability

SSDUP: a traffic-aware ssd burst buffer for HPC systems

libPRISM: an intelligent adaptation of prefetch and SMT levels

Packet coalescing exploiting data redundancy in GPGPU architectures

Content Provider	ACM Digital Library
Author	Kim, Kyung Hoon Kim, Eun Jung Boyapati, Rahul Huang, Jiayi Jin, Yuho Yum, Ki Hwan
Abstract	General Purpose Graphics Processing Units (GPGPUs) are becoming a cost-effective hardware approach for parallel computing. Many executions on the GPGPUs place heavy stress on the memory system, creating network bottlenecks near memory controllers. We observe that data redundancy in communication traffic is common-place across a wide range of GPGPU applications. To exploit the data redundancy, we propose a packet coalescing mechanism to alleviate the network bottlenecks by directly reducing the traffic volume. The key idea is to coalesce multiple packets into one without increasing the packet size when they carry redundant cache blocks. To ensure that the coalesced packets are delivered to their respective destinations, we adopt multicast routing for the interconnection network of GPGPUs. Our coalescing approach yields 15% IPC improvement (up to 112%) in a large-scale GPGPU with 2D mesh across various GPGPU applications, by reducing average memory access time (AMAT) by 15.5% (up to 65.2%) and obtaining network bandwidth savings by 13% (up to 37%). Also, our coalescing approach achieves 7% IPC improvement in the NVIDIA Fermi architecture with the crossbar.
Starting Page	1
Ending Page	10
Page Count	10
File Format	PDF
ISBN	9781450350204
DOI	10.1145/3079079.3079088
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-06-14
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multicast Inter-core locality Packet coalescing Gpgpu
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

The Case for Exploiting Packet Loss Locality in Multicast Loss Recovery (2002)

The Case for Exploiting Packet Loss Locality in Multicast Loss Recovery (2002)

The Case for Exploiting Packet Loss Locality in Multicast Loss Recovery (2002)

Control flow coalescing on a hybrid dataflow/von Neumann GPGPU

WarpPool: sharing requests with inter-warp coalescing for throughput processors

Analyzing locality of memory references in GPU architectures

Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement

Dinloop based inter-domain multicast with mpls.

Exploiting inter-thread temporal locality for chip multithreading (2010)

Packet coalescing exploiting data redundancy in GPGPU architectures

Similar Documents

The Case for Exploiting Packet Loss Locality in Multicast Loss Recovery (2002)

The Case for Exploiting Packet Loss Locality in Multicast Loss Recovery (2002)

The Case for Exploiting Packet Loss Locality in Multicast Loss Recovery (2002)

Control flow coalescing on a hybrid dataflow/von Neumann GPGPU

WarpPool: sharing requests with inter-warp coalescing for throughput processors

Analyzing locality of memory references in GPU architectures

Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement

Dinloop based inter-domain multicast with mpls.

Exploiting inter-thread temporal locality for chip multithreading (2010)

Packet coalescing exploiting data redundancy in GPGPU architectures