NDLI: Towards the design of fault-tolerant mixed-criticality systems on multicores

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Towards the design of fault-tolerant mixed-criticality systems on multicores

Content Provider	ACM Digital Library
Author	Thiele, Lothar Zeng, Luyuan Huang, Pengcheng
Abstract	Mixed-criticality is a significant recent trend in the embedded system industry, where common computing platforms are utilized to host functionalities of varying criticality levels. To date, most scheduling techniques have focused on the timing aspect of this problem, while functional safety (i.e. fault-tolerance) is often neglected. This paper presents design methodologies to guarantee both safety and schedulability for real-time mixed-criticality systems on identical multicores. Assuming hardware/software transient errors, we model safety requirements on different criticality levels explicitly according to safety standards; based on this, we further propose fault-tolerant mixed-criticality scheduling techniques with task replication and re-execution to enhance system safety. To cope with runtime urgencies where critical tasks do not succeed after a certain number of trials, our techniques can perform system reconfigurations (task killing or service degradation) in those situations to reallocate system resources to the critical tasks. Due to explicit modeling of safety, we can quantify the impact of task killing and service degradation on system feasibility (safety and schedulability), enabling a rigorous design. To this end, we derive analysis techniques when reconfigurations are triggered either globally (synchronously) on all cores or locally (asynchronously) on each core. To our best knowledge, this is the first work on fault-tolerant mixed-criticality scheduling on multicores, matching theoretical insights with industrial safety standards. Our proposed techniques are validated with an industrial application and extensive simulations.
Starting Page	1
Ending Page	10
Page Count	10
File Format	PDF
ISBN	9781450344821
DOI	10.1145/2968455.2968515
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-10-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multicores Reliability Modeling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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