NDLI: Improved SAT-based Boolean matching using implicants for LUT-based FPGAs

Please wait, while we are loading the content...

A routing fabric for monolithically stacked 3D-FPGA

A versatile, low latency HyperTransport core

Variation-aware routing for FPGAs

Synthesis of an application-specific soft multiprocessor system

High-level languages: the future or a passing fad?

Integrating FPGAs in high-performance computing: introduction

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

The shunt: an FPGA-based accelerator for network intrusion prevention

Design of a logic element for implementing an asynchronous FPGA

An FPGA-based Pentium® in a complete desktop system

Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation

FPGA-friendly code compression for horizontal microcoded custom IPs

Integrating FPGAs in high-performance computing: the architecture and implementation perspective

Power-aware FPGA logic synthesis using binary decision diagrams

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis

Attacking elliptic curve cryptosystems with special-purpose hardware

Designing efficient input interconnect blocks for LUT clusters using counting and entropy

A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA

Post-route LUT output polarity selection for timing optimization

A practical FPGA-based framework for novel CMP research

Integrating FPGAs in high-performance computing: programming models for parallel systems -- the programmer's perspective

GlitchLess: an active glitch minimization technique for FPGAs

Efficient hardware checkpointing: concepts, overhead analysis, and implementation

CReconfigurable finite field instruction set architecture

A synthesizable datapath-oriented embedded FPGA fabric

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs

Content Provider	ACM Digital Library
Author	Cong, Jason Minkovich, Kirill
Abstract	Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based Boolean matching formulation (SAT-BM-M) [11]. The principal improvement was achieved by deriving the SAT formulation using the implicant instead of minterm representation of the function to be matched. This enables our BM formulation to create a SAT problem of size O (as opposed to $O(m•2^{k})$ in the original formulation, where n is the number of inputs to the function, k is the size of the LUT, and m is the number of implicants, which is much smaller than 2 n and experimentally found to be around 3 . Using the new BM formulation, and considering 10-input functions, we can show an almost 3x run time improvement and can solve 5.6x more problems than the SAT-based BM formulation in [11]. Moreover, using this improved Boolean matching formulation, we implemented (as a proof of concept) a FPGA resynthesis tool, called RIMatch, which was able to reduce the number of LUTs produced by ZMap by 10% on the MCNC benchmarks.
Starting Page	139
Ending Page	147
Page Count	9
File Format	PDF
ISBN	9781595936004
DOI	10.1145/1216919.1216944
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-02-18
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Implicant Logic synthesis Fpga lookup table Sat Boolean matching
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimality study of logic synthesis for LUT-based FPGAs

Efficient SAT-based Boolean matching for FPGA technology mapping

Logic re-synthesis for fpgas by sat-based boolean matching ∗.

Logic Re-Synthesis for FPGAs by SAT-based Boolean Matching

Mapping and resynthesis for lut-based fpgas with an efficient sat-based boolean matching.

LUT-based FPGA technology mapping for reliability

A tutorial on logic synthesis for lookup-table based FPGAs

Mapping and Resynthesis for LUT-based FPGAs with an Efficient SAT-Based Boolean Matching

New approach of exploiting symmetry in SAT-based Boolean matching for FPGA technology mapping

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs

Similar Documents

Optimality study of logic synthesis for LUT-based FPGAs

Efficient SAT-based Boolean matching for FPGA technology mapping

Logic re-synthesis for fpgas by sat-based boolean matching ∗.

Logic Re-Synthesis for FPGAs by SAT-based Boolean Matching

Mapping and resynthesis for lut-based fpgas with an efficient sat-based boolean matching.

LUT-based FPGA technology mapping for reliability

A tutorial on logic synthesis for lookup-table based FPGAs

Mapping and Resynthesis for LUT-based FPGAs with an Efficient SAT-Based Boolean Matching

New approach of exploiting symmetry in SAT-based Boolean matching for FPGA technology mapping

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs