NDLI: New approach of exploiting symmetry in SAT-based Boolean matching for FPGA technology mapping

Content Provider	IEEE Xplore Digital Library
Author	Wang Xiu-qin Yang Yang
Copyright Year	2013
Description	Author affiliation: Coll. of Inf. Sci. & Technol., Bohai Univ., Jinzhou, China (Wang Xiu-qin) \|\| Coll. of Eng., Bohai Univ., Jinzhou, China (Yang Yang)
Abstract	Boolean matching is a key procedure in FPGA technology mapping. SAT-based Boolean matching provides a flexible solution for exploring various FPGA architectures. However, the computational complexity prohibits its application practically, inputs permutation is the bottleneck of SAT-based approach. In this paper, a new approach of exploiting symmetry in PLBs architecture and Boolean function is proposed. The problem of input permutation is transformed to the problem of combination assignment according to our three strategies, which directly generate necessary permutations and only check the satisfiability of these necessary permutations. The instances analysis shows that our approach can greatly reduce the problem scale and improve the performance of SAT-based Boolean matching. More experiments will be done, and more factors will be considered in future work.
Starting Page	282
Ending Page	285
File Size	243309
Page Count	4
File Format	PDF
ISBN	9781479903801
DOI	10.1109/ICVES.2013.6619648
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-07-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Boolean functions Design automation technology mapping symmetry FPGA SAT-based Educational institutions Table lookup Pins Field programmable gate arrays
Content Type	Text
Resource Type	Article

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