NDLI: High-level languages: the future or a passing fad?

Please wait, while we are loading the content...

A routing fabric for monolithically stacked 3D-FPGA

A versatile, low latency HyperTransport core

Variation-aware routing for FPGAs

Synthesis of an application-specific soft multiprocessor system

High-level languages: the future or a passing fad?

Integrating FPGAs in high-performance computing: introduction

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

The shunt: an FPGA-based accelerator for network intrusion prevention

Design of a logic element for implementing an asynchronous FPGA

An FPGA-based Pentium® in a complete desktop system

Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation

FPGA-friendly code compression for horizontal microcoded custom IPs

Integrating FPGAs in high-performance computing: the architecture and implementation perspective

Power-aware FPGA logic synthesis using binary decision diagrams

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis

Attacking elliptic curve cryptosystems with special-purpose hardware

Designing efficient input interconnect blocks for LUT clusters using counting and entropy

A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA

Post-route LUT output polarity selection for timing optimization

A practical FPGA-based framework for novel CMP research

Integrating FPGAs in high-performance computing: programming models for parallel systems -- the programmer's perspective

GlitchLess: an active glitch minimization technique for FPGAs

Efficient hardware checkpointing: concepts, overhead analysis, and implementation

CReconfigurable finite field instruction set architecture

A synthesizable datapath-oriented embedded FPGA fabric

High-level languages: the future or a passing fad?

Content Provider	ACM Digital Library
Author	Wirthlin, Mike Guyler, Andrew Burich, Misha Von Herzen, Brian
Abstract	There are several interesting compilation tools on the market for synthesizing FPGA circuits from "high" level languages. These tools advertise the ability to generate high-quality FPGA circuits from a variety of specification formats such procedural languages (C, Fortran, etc.), modeling languages (SystemC), or from signal flow graphs. These tools claim significant improvements in design productivity by allowing the designer to operate at higher levels of abstraction than available with traditional RTL-level synthesis.Some claim that these high-level tools will completely change the way we design FPGAs. Those with this view believe that these tools will replace today's design approaches and VHDL/Verilog design will "wither away" like assembly language programming. They believe that the FPGA designer of the future will only need basic programming skills to create a high-quality FPGA designs. The arcane RTL design methodology used today will be a thing of the past. Others believe that these tools are just another fad in the long line of failed high-level design tools. They suggest that procedural languages like C are ill-suited to express the fine-grain parallelism available in hardware. Further, the synchronization/timing semantics needed to implement parallel hardware are not available. Perhaps of most concern to those in this camp is the lower quality circuits synthesized by these tools. What good is a high-level tool if it can't meet your timing or performance constraint? If high-level tools are successful, those with this view believe they will be limited to small niche markets with limited appeal to the average designer.What is the future of FPGA design? Will higher-level design tools finally provide the productivity and quality that has been promised? Or, are these tools just another passing fad? This panel will address these questions and discuss the future FPGA design. The panel will include experts from a variety of perspectives including representatives from high-level tool vendors, FPGA manufacturers, and experienced designers. Each panelist will give a brief summary of their views on this topic, followed by questions and lively debate. Audience participation is actively encouraged and audience members will have the opportunity for asking questions and making statements.
Starting Page	127
Ending Page	127
Page Count	1
File Format	PDF
ISBN	9781595936004
DOI	10.1145/1216919.1216938
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-02-18
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Rtl design High-level design languages
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Hardware synthesis of high-level C constructs

Going Mainstream or Just a Passing Fad? The Future of the Ancestral Health Movement

Source-Level Compiler Optimizations for High-Level Synthesis

Parallel Database Systems: The Future of Database Processing or a Passing Fad? (1991)

A step towards intelligent translation from high-level design to RTL

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

2009 ENID GRAHAM MEMORIAL LECTURE Inter-professional Collaboration: Passing Fad or Way of the Future?

A method for the generation of HDL code at the RTL level from a high-level formal specification language

Inter-professional collaboration: passing fad or way of the future?

High-level languages: the future or a passing fad?

Similar Documents

Hardware synthesis of high-level C constructs

Going Mainstream or Just a Passing Fad? The Future of the Ancestral Health Movement

Source-Level Compiler Optimizations for High-Level Synthesis

Parallel Database Systems: The Future of Database Processing or a Passing Fad? (1991)

A step towards intelligent translation from high-level design to RTL

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

2009 ENID GRAHAM MEMORIAL LECTURE Inter-professional Collaboration: Passing Fad or Way of the Future?

A method for the generation of HDL code at the RTL level from a high-level formal specification language

Inter-professional collaboration: passing fad or way of the future?

High-level languages: the future or a passing fad?