NDLI: SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations

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FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access

Transactional Memory Architecture and Implementation for IBM System Z

Warped-DMR: Light-weight Error Detection for GPGPU

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults

NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures

Cache-Conscious Wavefront Scheduling

Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor

Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation

KnightShift: Scaling the Energy Proportionality Wall through Server-Level Heterogeneity

Rethinking DRAM Power Modes for Energy Proportionality

CoScale: Coordinating CPU and Memory System DVFS in Server Systems

Predicting Performance Impact of DVFS for Realistic Memory Systems

Vector Extensions for Decision Support DBMS Acceleration

NOC-Out: Microarchitecting a Scale-Out Processor

SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

AUDIT: Stress Testing the Automatic Way

Accurate Fine-Grained Processor Power Proxies

Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

CoLT: Coalesced Large-Reach TLBs

NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers

Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance

Addressing End-to-End Memory Access Latency in NoC-Based Multicores

MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

Composite Cores: Pushing Heterogeneity Into a Core

Control-Flow Decoupling

Spatiotemporal Coherence Tracking

Predicting Coherence Communication by Tracking Synchronization Points at Run Time

Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

Improving Cache Management Policies Using Dynamic Reuse Distances

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem

Inferred Models for Dynamic and Sparse Hardware-Software Spaces

SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations

Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and Optimization

Neural Acceleration for General-Purpose Approximate Programs

Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator

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SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations

Content Provider	ACM Digital Library
Author	Wu, Youfeng Wang, Cheng Park, Hyunchul Rong, Hongbo
Abstract	Traditional alias analysis is expensive and ineffective for dynamic optimizations. In practice, dynamic optimization systems perform memory optimizations speculatively, and rely on hardware, such as alias registers, to detect memory aliases at runtime. Existing hardware alias detection schemes either cannot scale up to a large number of alias registers or may introduce false positives. Order-based alias detection overcomes the limitations. However, it brings considerable challenges as how software can efficiently manage the alias register queue and impose restrictions on optimizations. In this paper, we present SMARQ, a Software-Managed Alias Register Queue, which manages the alias register queue efficiently and supports more aggressive speculative optimizations. We conducted experiments with a dynamic optimization system on a VLIW processor that has 64 alias registers. The experiments on a suite of SPECFP2000 benchmarks show that SMARQ improves the overall performance by 39% as compared to the case without hardware alias detection. By scaling up to a large number (from 16 to 64) of alias registers, SMARQ improves performance by 10%. Compared to a technique with false positives (similar to Itanium), SMARQ improves performance by 13%. To reduce the chance of alias register overflow, the novel alias register allocation algorithm in SMARQ reduces the alias register working set by 74% as compared to a straightforward alias register allocation based on program order.
Starting Page	425
Ending Page	436
Page Count	12
File Format	PDF
ISBN	9780769549248
ISSN	10724451
DOI	10.1109/MICRO.2012.46
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-12-01
Access Restriction	Subscribed
Subject Keyword	Dynamic optimization alias register hardware alias detection speculation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations

Enabling Efficient Alias Speculation

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Optimizing Caching DSM for Distributed Software Speculation

Facilitating compiler optimizations through the dynamic mapping of alternate register structures

Enabling Efficient Alias Speculation

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SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations

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SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations