NDLI: Composite Cores: Pushing Heterogeneity Into a Core

Please wait, while we are loading the content...

Message from the General Chair

Message from the Program Chair

External Review Committee

FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access

Transactional Memory Architecture and Implementation for IBM System Z

Warped-DMR: Light-weight Error Detection for GPGPU

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults

NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures

Cache-Conscious Wavefront Scheduling

Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor

Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation

KnightShift: Scaling the Energy Proportionality Wall through Server-Level Heterogeneity

Rethinking DRAM Power Modes for Energy Proportionality

CoScale: Coordinating CPU and Memory System DVFS in Server Systems

Predicting Performance Impact of DVFS for Realistic Memory Systems

Vector Extensions for Decision Support DBMS Acceleration

NOC-Out: Microarchitecting a Scale-Out Processor

SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

AUDIT: Stress Testing the Automatic Way

Accurate Fine-Grained Processor Power Proxies

Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

CoLT: Coalesced Large-Reach TLBs

NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers

Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance

Addressing End-to-End Memory Access Latency in NoC-Based Multicores

MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

Composite Cores: Pushing Heterogeneity Into a Core

Control-Flow Decoupling

Spatiotemporal Coherence Tracking

Predicting Coherence Communication by Tracking Synchronization Points at Run Time

Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

Improving Cache Management Policies Using Dynamic Reuse Distances

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem

Inferred Models for Dynamic and Sparse Hardware-Software Spaces

SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations

Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and Optimization

Neural Acceleration for General-Purpose Approximate Programs

Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator

Publisher's Information

Composite Cores: Pushing Heterogeneity Into a Core

Content Provider	ACM Digital Library
Author	Sleiman, Faissal M. Wenisch, Thomas F. Das, Reetuparna Padmanabha, Shruti Lukefahr, Andrew Dreslinski, Ronald Mahlke, Scott
Abstract	Heterogeneous multicore systems -- comprised of multiple cores with varying capabilities, performance, and energy characteristics --have emerged as a promising approach to increasing energy efficiency. Such systems reduce energy consumption by identifying phase changes in an application and migrating execution to the most efficient core that meets its current performance requirements. However, due to the overhead of switching between cores, migration opportunities are limited to coarse-grained phases (hundreds of millions of instructions), reducing the potential to exploit energy efficient cores. We propose Composite Cores, an architecture that reduces switching overheads by bringing the notion of heterogeneity within a single core. The proposed architecture pairs big and little compute µEngines that together can achieve high performance and energy efficiency. By sharing much of the architectural state between the µEngines, the switching overhead can be reduced to near zero, enabling fine-grained switching and increasing the opportunities to utilize the little µEngine without sacrificing performance. An intelligent controller switches between the µEngines to maximize energy efficiency while constraining performance loss to a configurable bound. We evaluate Composite Cores using cycle accurate micro architectural simulations and a detailed power model. Results show that, on average, the controller is able to map 25% of the execution to the little µEngine, achieving an 18% energy savings while limiting performance loss to 5%.
Starting Page	317
Ending Page	328
Page Count	12
File Format	PDF
ISBN	9780769549248
ISSN	10724451
DOI	10.1109/MICRO.2012.37
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-12-01
Access Restriction	Subscribed
Subject Keyword	Heterogeneous architecture core microarchitecure split pipelines reactive controller
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in