NDLI: Warped-DMR: Light-weight Error Detection for GPGPU

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Message from the General Chair

Message from the Program Chair

External Review Committee

Reviewers

FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access

Transactional Memory Architecture and Implementation for IBM System Z

Warped-DMR: Light-weight Error Detection for GPGPU

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults

NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures

Cache-Conscious Wavefront Scheduling

Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor

Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation

KnightShift: Scaling the Energy Proportionality Wall through Server-Level Heterogeneity

Rethinking DRAM Power Modes for Energy Proportionality

CoScale: Coordinating CPU and Memory System DVFS in Server Systems

Predicting Performance Impact of DVFS for Realistic Memory Systems

Vector Extensions for Decision Support DBMS Acceleration

NOC-Out: Microarchitecting a Scale-Out Processor

SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

AUDIT: Stress Testing the Automatic Way

Accurate Fine-Grained Processor Power Proxies

Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

CoLT: Coalesced Large-Reach TLBs

NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers

Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance

Addressing End-to-End Memory Access Latency in NoC-Based Multicores

MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

Composite Cores: Pushing Heterogeneity Into a Core

Control-Flow Decoupling

Spatiotemporal Coherence Tracking

Predicting Coherence Communication by Tracking Synchronization Points at Run Time

Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

Improving Cache Management Policies Using Dynamic Reuse Distances

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem

Inferred Models for Dynamic and Sparse Hardware-Software Spaces

SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations

Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and Optimization

Neural Acceleration for General-Purpose Approximate Programs

Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator

Author Index

Publisher's Information

Warped-DMR: Light-weight Error Detection for GPGPU

Content Provider	ACM Digital Library
Author	Annavaram, Murali Jeon, Hyeran
Abstract	General purpose graphics processing units (GPGPUs) are feature rich GPUs that provide general purpose computing ability with massive number of parallel threads. The massive parallelism combined with programmability made GPGPUs the most attractive choice in supercomputing centers. Unsurprisingly, most of the GPGPU-based studies have been focusing on performance improvement leveraging GPGPU's high degree of parallelism. However, for many scientific applications that commonly run on supercomputers, program correctness is as important as performance. Few soft or hard errors could lead to corrupt results and can potentially waste days or even months of computing effort. In this research we exploit unique architectural characteristics of GPGPUs to propose a light weight error detection method, called Warped Dual Modular Redundancy (Warped-DMR). Warped-DMR detects errors in computation by relying on opportunistic spatial and temporal dual-modular execution of code. Warped-DMR is light weight because it exploits the underutilized parallelism in GPGPU computing for error detection. Error detection spans both within a warp as well as between warps, called intra-warp and inter-warp DMR, respectively. Warped-DMR achieves 96% error coverage while incurring a worst-case 16% performance overhead without extra execution units or programmer's effort.
Starting Page	37
Ending Page	47
Page Count	11
File Format	PDF
ISBN	9780769549248
ISSN	10724451
DOI	10.1109/MICRO.2012.13
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-12-01
Access Restriction	Subscribed
Subject Keyword	Gpgpu dmr reliable computing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Warped-DMR: Light-weight Error Detection for GPGPU

Dynamically adaptive and reliable approximate computing using light-weight error analysis

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Warped-DMR: Light-weight Error Detection for GPGPU

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