NDLI: Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits

Please wait, while we are loading the content...

CAD for displays!

Reliable system design: models, metrics and design techniques

Challenges at 45nm and beyond

More Moore: foolish, feasible, or fundamentally different?

Network flow-based power optimization under timing constraints in MSV-driven floorplanning

Synthesis from multi-cycle atomic actions as a solution to the timing closure problem

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification

MAPS: multi-algorithm parallel circuit simulation

Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure

Verification of arithmetic datapaths using polynomial function models and congruence solving

System-level power estimation using an on-chip bus performance monitoring unit

Efficient block-based parameterized timing analysis covering all potentially critical paths

Pyramids: an efficient computational geometry-based approach for timing-driven placement

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits

System-level thermal aware design of applications with uncertain execution time

Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design

Design and optimization of a digital microfluidic biochip for protein crystallization

Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example

NTHU-Route 2.0: a fast and stable global router

Race analysis for SystemC using model checking

SRAM dynamic stability: theory, variability and analysis

Physical models for electron transport in graphene nanoribbons and their junctions

Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization

Correct-by-construction microarchitectural pipelining

Layout decomposition for double patterning lithography

BSG-Route: a length-matching router for general topology

Evaluation of voltage interpolation to address process variations

Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors

Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches

ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits

Statistical path selection for at-speed test

Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms

Lightweight secure PUFs

Process variability-aware transient fault modeling and analysis

Robust FPGA resynthesis based on fault-tolerant Boolean matching

Guaranteed stable projection-based model reduction for indefinite and unstable linear systems

Integrated circuit design with NEM relays

Using test data to improve IC quality and yield

Incorporating logic exclusivity (LE) constraints in noise analysis using gain guided backtracking method

Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysis

What can brain researchers learn from computer engineers and vice versa?

Architecting parallel programs

Mixed-signal simulation challenges and solutions

Linear constraint graph for floorplan optimization with soft blocks

To SAT or not to SAT: Ashenhurst decomposition in a large scale

Temperature-aware test scheduling for multiprocessor systems-on-chip

Yield-aware hierarchical optimization of large analog integrated circuits

Delay-optimal simultaneous technology mapping and placement with applications to timing optimization

Automated abstraction by incremental refinement in interpolant-based model checking

Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing

Adjustment-based modeling for statistical static timing analysis with high dimension of variability

Guiding global placement with wire density

A novel sequential circuit optimization with clock gating logic

Proactive temperature balancing for low cost thermal management in MPSoCs

Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits

Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction

Breaking the simulation barrier: SRAM evaluation through norm minimization

FastRoute3.0: a fast and high quality global router based on virtual capacity

MC-Sim: an efficient simulation tool for MPSoC designs

Impulse sensitivity function analysis of periodic circuits

Characterization and modeling of graphene field-effect devices

Decoupling capacitance allocation for timing with statistical noise model and timing analysis

Performance optimization of elastic systems using buffer resizing and buffer insertion

Electrically driven optical proximity correction based on linear programming

Double patterning technology friendly detailed routing

Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors

SPM management using Markov chain based data access prediction

On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications

Parameterized transient thermal behavioral modeling for chip multiprocessors

Power supply signal calibration techniques for improving detection resolution to hardware Trojans

Efficient and accurate eye diagram prediction for high speed signaling

Hardware protection and authentication through netlist level obfuscation

STEEL: a technique for stress-enhanced standard cell library design

Fault tolerant placement and defect reconfiguration for nano-FPGAs

Sparse implicit projection (SIP) for reduction of general many-terminal networks

Module locking in biochemical synthesis

Silicon feedback to improve frequency of high-performance microprocessors: an overview

Constrained aggressor set selection for maximum coupling noise

Smoothed form of nonlinear phase macromodel for oscillators

Embedded software verification: challenges and solutions

A novel fixed-outline floorplanner with zero deadspace for hierarchical design

Boolean factoring and decomposition of logic networks

On capture power-aware test data compression for scan-based testing

Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems

PaRS: fast and near-optimal grid-based cell sizing for library-based design

A succinct memory model for automated design debugging

Accurate energy breakeven time estimation for run-time power gating

Post-silicon timing characterization by compressed sensing

Constraint graph-based macro placement for modern mixed-size circuit designs

Scalable and scalably-verifiable sequential synthesis

A framework for predictive dynamic temperature management of microprocessor systems

A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects

Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions

Power supply noise aware workload assignment for multi-core systems

Multi-layer global routing considering via and wire capacities

Verifying external interrupts of embedded microprocessor in SoC with on-chip bus

Automated extraction of expert knowledge in analog topology selection and sizing

Graphene nanoribbon FETs: technology exploration and CAD

Transition-aware decoupling-capacitor allocation in power noise reduction

Performance estimation and slack matching for pipelined asynchronous architectures with choice

A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique

Routing for chip-package-board co-design considering differential pairs

ROAdNoC: runtime observability for an adaptive network on chip architecture

Process variation aware system-level task allocation using stochastic ordering of delay distributions

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links

Temperature aware task sequencing and voltage scaling

Path-RO: a novel on-chip critical path delay measurement under process variations

A capacitance solver for incremental variation-aware extraction

MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm

A statistical approach for full-chip gate-oxide reliability analysis

Thermal-aware reliability analysis for platform FPGAs

Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method

Robust reconfigurable filter design using analytic variability quantification techniques

Context-sensitive static transistor-level IR analysis

Comprehensive procedure for fast and accurate coupled oscillator network simulation

Nanolithography and CAD challenges for 32nm/22nm and beyond

On the numbers of variables to represent sparse logic functions

A polynomial time approximation scheme for timing constrained minimum cost layer assignment

The analysis of cyclic circuits with Boolean satisfiability

Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits

Practical, fast Monte Carlo statistical static timing analysis: why and how

A voltage-frequency island aware energy optimization framework for networks-on-chip

Linear analysis of random process variability

Importance sampled circuit learning ensembles for robust analog IC design

Placement based multiplier rewiring for cell-based designs

Diastolic arrays: throughput-driven reconfigurable computing

Overlay aware interconnect and timing variation modeling for double patterning technology

Area-I/O flip-chip routing for chip-package co-design

FBT: filled buffer technique to reduce code size for VLIW processors

Game-theoretic timing analysis

On the decreasing significance of large standard cells in technology mapping

On efficient Monte Carlo-based statistical static timing analysis of digital circuits

Exact basic geometric operations on arbitrary angle polygons using only fixed size integer coordinates

Obstacle-avoiding rectilinear Steiner tree construction

Advancing supercomputer performance through interconnection topology synthesis

Integrated code and data placement in two-dimensional mesh based chip multiprocessors

Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits

Content Provider	ACM Digital Library
Author	Li, Yiming Yeh, Ta-Ching Hwang, Chih-Hong Li, Tien-Yeh
Abstract	Modeling of device variability is crucial for the accuracy of timing in circuits and systems, and the stability of high-frequency application. Unfortunately, due to the randomness of dopant position in device, the fluctuation of device gate capacitance is nonlinear and hard to be modeled in current compact models. Therefore, a large-scale statistically sound "atomistic" device/circuit coupled simulation approach is proposed to characterize the random-dopant-induced characteristic fluctuations in 16-nm-gate CMOS integrated circuits concurrently capturing the discrete-dopant-number- and discrete-dopant-position-induced fluctuations. The variations of transition time of digital circuit (inverter, NAND, and NOR gates) and high-frequency characteristic of common-source amplifier are estimated. For the digital circuits, the function-dependent and circuit-topology-dependent characteristic fluctuations resulted from random nature of discrete dopants is for the first time discussed. This study provides an insight into random-dopant- induced intrinsic timing and high-frequency characteristic fluctuations. The accuracy of the simulation technique is confirmed by the use of experimentally calibrated transistor physical model.
Starting Page	278
Ending Page	285
Page Count	8
File Format	PDF
ISBN	9781424428205
ISSN	10923152
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-11-10
Access Restriction	Subscribed
Subject Keyword	Device variability Fluctuation High frequency circuit Digital circuit Random dopant Timing
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software Computer Science Applications

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in