NDLI: Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit

Content Provider	IEEE Xplore Digital Library
Author	Yiming Li Chih-Hong Hwang Tien-Yeh Li
Copyright Year	2004
Abstract	As the dimensions of semiconductor devices continue to be reduced, device fluctuations have become critical to determining the accuracy of timing in circuits and systems. This brief studies the discrete-dopant-induced timing characteristic fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits using a 3-D ldquoatomisticrdquo coupled device-circuit simulation. The accuracy of the simulation has been confirmed by using the experimentally calibrated transistor physical model. For a 16-nm-gate CMOS inverter, 3.5%, 2.4%, 18.3%, and 13.2% normalized fluctuations in the rise time, fall time, high-to-low delay time, and low-to-high delay time, respectively, are found. Random dopants may cause significant timing fluctuations in the studied circuits. Suppression approaches that are based on the circuit and device design viewpoints are implemented to examine the associated characteristic fluctuations. The use of shunted transistors in the circuit provides similar suppression to the use of a device with doubled width. However, both approaches increase the chip area. To eliminate the need to increase the chip area, channel engineering approaches (vertical and lateral) are proposed, and their effectiveness in reducing the timing fluctuation is demonstrated.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	379
Ending Page	383
Page Count	5
File Size	677487
File Format	PDF
ISSN	15497747
Volume Number	56
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Fluctuations Circuit simulation Delay effects Semiconductor devices Accuracy Circuits and systems Coupling circuits Semiconductor device modeling Semiconductor process modeling timing fluctuation Fluctuation suppression technique modeling and simulation nanometer-scale metal–oxide–semiconductor field-effect transistor (MOSFET) device and circuit random dopant effect
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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