NDLI: A framework for layout-level logic restructuring

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A framework for layout-level logic restructuring

Content Provider	ACM Digital Library
Author	Lillis, John Kim, Hosung Leo
Abstract	It is well known that optimizations made by traditional logic synthesis tools often correlate poorly with post-layout performance; this is largely a result of interconnect effects only visible after layout. As a result, several attempts at physically aware logic synthesis have been made (e.g.,[2], [9], [14], [4], [7], [12], [16], [15]). In this paper a corrective methodology is proposed for timing-driven logic restructuring at the placement level; the approach currently focuses on LUT-based FPGAs. Driven by placement level static timing analysis, the method induces relatively large, timing-critical fan-in trees via (temporary) replication as in [9]. Such trees are then reimplemented where the degrees of freedom include functional decomposition of LUTs, subject graph covering/mapping, and physical embedding. A dynamic programming algorithm optimizes over all of these freedoms simultaneously. All simple disjoint decompositions (i.e., Ashenhurst style) are encoded in the subject tree/graph using choice nodes similar to those in [11]. At the same time, because embedding is done simultaneously, interconnect delay is directly taken into account We have implemented the framework and in many cases we were able to approach a fixed flip-flop lower-bound on achievable clock period. Promising experimental results are reported with average 14.8% (up to 37.4%) clock period reduction compared with the timing-driven placement from VPR [13] and average 6.6% (upto 17%) reduction compared with the basic fan-in tree embedder from [9].
Starting Page	87
Ending Page	94
Page Count	8
File Format	PDF
ISBN	9781605580487
DOI	10.1145/1353629.1353652
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-04-13
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Timing optimization Logic resynthesis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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