| Abstract |
True manufacturing-aware design, or "MAD", is urgently needed in light of increasing pitch, variability, leakage and reliability challenges. This talk will present directions in physical design and performance analysis that comprise "real MAD" for 45nm and below. Following are four examples. (1) Methodology for guardband exploitation. Model guardbands supplied by silicon vendors can no longer be passively applied by semiconductor product companies in design flows. MAD requires improved understanding â and exploitation â of how guardbands modulate QOR and turnaround time of SP&R implementation flows. In particular, model guardbands are a potential lever for diecost reduction, via a tradeoff of loss in parametric yield (scrapoff)versus gain in raw die per wafer. (2) Enablement of double-patterning lithography (DPL). Double patterning involves partitioning of dense circuit patterns into two separate exposures, such that decreased pattern density in each exposure can improve resolution and depth of focus (DOF). Barring unforeseen rapid adoption of restricted layout practices, DPL is likely to play a more important role than previously anticipated, since lithography alternatives such as hyper-NA immersion lithography and EUV are continually delayed. On the other hand, DPL increases manufacturing cost in fundamental ways that include (i) reduction of throughput, (ii) complexity of litho-etch process control, (iii) generation of excess line-ends, and (iv) requirements for tight overlay control. With this in mind, MAD requires new methods for DPL layout decomposition and coloring assignment that comprehend performance and yield impacts of line-end shortening, corner rounding, misalignment (overlay), as well as both inter- and intra-exposure proximity effects. Methods for layout perturbation to cure hotspots are likely also required. On the modeling and analysis side, DPL presents a host of technical and methodological challenges that stem from "the bimodal problem": devices are drawn from two distinct distributions (corresponding to the two exposure steps) that each exhibit spatial correlations, but with no correlation between the exposures (3) Design for equipment. MAD must ultimately be aware of characteristics of the processing equipment used in the foundry. Opportunities abound with respect to the mask flow (fracture- and mask write-aware layout design), the BEOL stack (CMP-aware layout design), and step-and-scan lithography tools (asymmetry of overlay tolerances, and tunable overlay error compensation). A technique of particular interest exploits the recent availability of fine-grain exposure dose control in the stepper to achieve both design-time (placement) and manufacturing-time (yield-aware dose mapping) optimizations of timing yield and leakage power. Indeed, placement and dose map co-optimization can simultaneously improve both timing yield and leakage power of a given design; the placement-aware dose map optimization is formulated as a quadratic optimization, and the complementary dose map-aware placement optimization is performed using an incremental placement heuristic. Near-maximal improvements in clock frequency can be achieved with essentially zero leakage power degradation (4) Glue P&R technologies. At 45nm and below, the traditional implementation flow will reclaim much of the functionality (via doubling, wire spreading, dummy fill insertion, pattern hotspot mitigation, parametric yield optimization) that was temporarily ceded at 65nm to post-GDS, physical verification-based subflows. Identifying the correct flow stage (e.g., placement or routing) at which to solve manufacturability problems depends on a mindset of "opportunism, at the right time" â that is, when enough information is available, and before doing work that will be thrown away. A well-known example: the appropriate juncture for correction of poly-layer litho hotspots is after detailed placement, but before routing. This is the basis of techniques that improve lithographic process window, leakage variability, timing yield, or other objectives by perturbing detailed placement within the flexibility afforded by placement whitespace. |
