NDLI: Implications of device timing variability on full chip timing

Content Provider	ACM Digital Library
Author	Annavaram, Murali Grochowski, Ed Reed, Paul
Abstract	As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This talk presents a quantitative evaluation of how low level device timing variations impact the timing at the functional block level. We evaluate two types of timing variations: random and systematic variations. The study introduces random and systematic timing variations to several functional blocks in Intel® Core™ Duo microprocessor design database and measures the resulting timing margins. The primary conclusion of this research is that as a result of combining two probability distributions (the distribution of the random variation and the distribution of path timing margins) functional block timing margins degrade non-linearly with increasing variability.
Starting Page	68
Ending Page	68
Page Count	1
File Format	PDF
ISBN	9781605580487
DOI	10.1145/1353629.1353644
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-04-13
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Implications of device timing variability on full chip timing