NDLI: Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors

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Architecture for Protecting Critical Secrets in Microprocessors

High Efficiency Counter Mode Security Architecture via Prediction and Precomputation

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions

Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management

Direct Cache Access for High Bandwidth Network I/O

Deconstructing Commodity Storage Clusters

A Robust Main-Memory Compression Scheme

Continuous Optimization

RENO: A Rename-Based Instruction Optimizer

A High Throughput String Matching Architecture for Intrusion Detection and Prevention

A Tree Based Router Search Engine Architecture with Single Port Memories

An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems

Design and Evaluation of Hybrid Fault-Detection Systems

Rescue: A Microarchitecture for Testability and Defect Tolerance

Opportunistic Transient-Fault Detection

An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures

Energy Optimization of Subthreshold-Voltage Sensor Network Processors

An Ultra Low Power System Architecture for Sensor Network Applications

Temporal Streaming of Shared Memory

RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence

Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking

Improving Program Efficiency by Packing Instructions into Registers

An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors

BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging

Mitigating Amdahl's Law through EPI Throttling

Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines

Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors

Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors

Optimizing Replication, Communication, and Capacity Allocation in CMPs

Techniques for Efficient Processing in Runahead Execution Engines

Piecewise Linear Branch Prediction

Analysis of the O-GEometric History Length Branch Predictor

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling

Microarchitecture of a High-Radix Router

Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks

Scalable Load and Store Processing in Latency Tolerant Processors

Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization

Store Buffer Design in First-Level Multibanked Data Caches

Dynamic Verification of Sequential Consistency

Virtualizing Transactional Memory

The Impact of Performance Asymmetry in Emerging Multicore Architectures

Exploiting Structural Duplication for Lifetime Reliability Enhancement

Computing Architectural Vulnerability Factors for Address-Based Structures

The V-Way Cache: Demand Based Associativity via Global Replacement

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Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors

Content Provider	ACM Digital Library
Author	Shafi, Hazim Zhang, Lixin Speight, Evan Rajamony, Ram
Abstract	With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor cores, varying amounts of level 1 and level 2 caching, and on-chip directory structures for level 3 caches and memory. The level 3 cache may be used as a victim cache for both modified and clean lines evicted from on-chip level 2 caches. Efficient area and performance management of this cache hierarchy is paramount given the projected increase in access latency to off-chip memory. This paper proposes simple architectural extensions and adaptive policies for managing the L2 and L3 cache hierarchy in a CMP system. In particular, we evaluate two mechanisms that improve cache effectiveness. First, we propose the use of a small history table to provide hints to the L2 caches as to which lines are resident in the L3 cache. We employ this table to eliminate some unnecessary clean write backs to the L3 cache, reducing pressure on the L3 cache and utilization of the on-chip bus. Second, we examine the performance benefits of allowing write backs from L2 caches to be placed in neighboring, on-chip L2 caches rather than forcing them to be absorbed by the L3 cache. This not only reduces the capacity pressure on the L3 cache but also makes subsequent accesses faster since L2-to-L2 cache transfers have typically lower latencies than accesses to a large L3 cache array. We evaluate the performance improvement of these two designs, and their combined effect, on four commercial workloads and observe a reduction in the overall execution time of up to 13%.
Starting Page	346
Ending Page	356
Page Count	11
File Format	PDF
ISBN	076952270X
ISSN	10636897
DOI	10.1109/ISCA.2005.8
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-06-04
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors

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