NDLI: Opportunistic Transient-Fault Detection

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Architecture for Protecting Critical Secrets in Microprocessors

High Efficiency Counter Mode Security Architecture via Prediction and Precomputation

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions

Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management

Direct Cache Access for High Bandwidth Network I/O

Deconstructing Commodity Storage Clusters

A Robust Main-Memory Compression Scheme

Continuous Optimization

RENO: A Rename-Based Instruction Optimizer

A High Throughput String Matching Architecture for Intrusion Detection and Prevention

A Tree Based Router Search Engine Architecture with Single Port Memories

An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems

Design and Evaluation of Hybrid Fault-Detection Systems

Rescue: A Microarchitecture for Testability and Defect Tolerance

Opportunistic Transient-Fault Detection

An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures

Energy Optimization of Subthreshold-Voltage Sensor Network Processors

An Ultra Low Power System Architecture for Sensor Network Applications

Temporal Streaming of Shared Memory

RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence

Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking

Improving Program Efficiency by Packing Instructions into Registers

An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors

BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging

Mitigating Amdahl's Law through EPI Throttling

Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines

Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors

Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors

Optimizing Replication, Communication, and Capacity Allocation in CMPs

Techniques for Efficient Processing in Runahead Execution Engines

Piecewise Linear Branch Prediction

Analysis of the O-GEometric History Length Branch Predictor

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling

Microarchitecture of a High-Radix Router

Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks

Scalable Load and Store Processing in Latency Tolerant Processors

Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization

Store Buffer Design in First-Level Multibanked Data Caches

Dynamic Verification of Sequential Consistency

Virtualizing Transactional Memory

The Impact of Performance Asymmetry in Emerging Multicore Architectures

Exploiting Structural Duplication for Lifetime Reliability Enhancement

Computing Architectural Vulnerability Factors for Address-Based Structures

The V-Way Cache: Demand Based Associativity via Global Replacement

Opportunistic Transient-Fault Detection

Content Provider	ACM Digital Library
Author	Vijaykumar, T. N. Gomaa, Mohamed A.
Abstract	CMOS scaling increases susceptibility of microprocessors to transient faults. Most current proposals for transient-fault detection use full redundancy to achieve perfect coverage while incurring significant performance degradation. However, most commodity systems do not need or provide perfect coverage. A recent paper explores this leniency to reduce the soft-error rate of the issue queue during L2 misses while incurring minimal performance degradation. Whereas the previous paper reduces soft-error rate without using any redundancy, we target better coverage while incurring similarly-minimal performance degradation by opportunistically using redundancy. We propose two semi-complementary techniques, called partial explicit redundancy (PER) and implicit redundancy through reuse (IRTR), to explore the trade-off between soft-error rate and performance. PER opportunistically exploits low-ILP phases and L2 misses to introduce explicit redundancy with minimal performance degradation. Because PER covers the entire pipeline and exploits not only L2 misses but all low-ILP phases, PER achieves better coverage than the previous work. To achieve coverage in high-ILP phases as well, we propose implicit redundancy through reuse (IRTR). Previous work exploits the phenomenon of instruction reuse to avoid redundant execution while falling back on redundant execution when there is no reuse. IRTR takes reuse to the extreme of performance-coverage trade-off and completely avoids explicit redundancy by exploiting reuseýs implicit redundancy within the main thread for fault detection with virtually no performance degradation. Using simulations with SPEC2000, we show that PER and IRTR achieve better trade-off between soft-error rate and performance degradation than the previous schemes.
Starting Page	172
Ending Page	183
Page Count	12
File Format	PDF
ISBN	076952270X
ISSN	10636897
DOI	10.1109/ISCA.2005.38
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-06-04
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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