NDLI: Store Buffer Design in First-Level Multibanked Data Caches

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Store Buffer Design in First-Level Multibanked Data Caches

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Store Buffer Design in First-Level Multibanked Data Caches

Content Provider	ACM Digital Library
Author	Llaberia, J. M. Ibanez, P. Torres, E. F. Vinals, V.
Abstract	This paper focuses on how to design a Store Buffer (STB) well suited to first-level multibanked data caches. Our goal is to forward data from in-flight stores to dependent loads with the latency of a cache bank. For that we propose a particular two-level STB design in which forwarding is done speculatively from a distributed first-level STB made of extremely small banks, while a centralized, second-level STB enforces correct store-load ordering a few cycles later. To that end we have identified several important design decisions: i) delaying allocation of first-level STB entries until stores execute, ii) deallocating first-level STB entries before stores commit, and iii) selecting a recovery policy well-matched to data forwarding misspeculations. Moreover, the two-level STB admits two enhancements that simplify the design leaving performance almost unchanged: i) removing the data forwarding capability from the second-level STB, and ii) not checking instruction age in first-level STB prior to forwarding data to loads. Following our guidelines and running SPECint-2K over an 8-way out-of-order processor, a two-level STB (first level with four STB banks of 8 entries each) performs similarly to an ideal, single-level STB with 128-entry banks working at the first-level cache latency.
Starting Page	469
Ending Page	480
Page Count	12
File Format	PDF
ISBN	076952270X
ISSN	10636897
DOI	10.1109/ISCA.2005.47
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-06-04
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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