NDLI: A fast layer elimination approach for power grid reduction

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A fast layer elimination approach for power grid reduction

Content Provider	ACM Digital Library
Author	Najm, Farid N. Yassine, Abdul-Amir
Abstract	Simulation and verification of the on-die power delivery network (PDN) is one of the key steps in the design of integrated circuits (ICs). With the very large sizes of modern grids, verification of PDNs has become very expensive and a host of techniques for faster simulation and grid model approximation have been proposed. These include topological node elimination, as in TICER and full-blown numerical model order reduction (MOR) as in PRIMA and related methods. However, both of these traditional approaches suffer from certain drawbacks that make them expensive and limit their scalability to very large grids. In this paper, we propose a novel technique for grid reduction that is a hybrid of both approaches---the method is numerical but also factors in grid topology. It works by eliminating whole internal layers of the grid at a time, while aiming to preserve the dynamic behavior of the resulting reduced grid. Effectively, instead of traditional node-by-node topological elimination we provide a numerical layer-by-layer block-matrix approach that is both fast and accurate. Experimental results show that this technique is capable of handling very large power grids and provides a 4.25x speed-up in transient analysis.
Starting Page	1
Ending Page	8
Page Count	8
File Format	PDF
ISBN	9781450344661
DOI	10.1145/2966986.2966989
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-11-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Model order reduction Graph sparsification Power grid
Content Type	Text
Resource Type	Article

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