NDLI: A flash-based digital circuit design flow

Please wait, while we are loading the content...

Scope - quality retaining display rendering workload scaling based on user-smartphone distance

NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory

Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip

Fast generation of lexicographic satisfiable assignments: Enabling canonicity in SAT-based applications

Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits

A flash-based digital circuit design flow

MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes

OWARU: free space-aware timing-driven incremental placement

Detailed placement for modern FPGAs using 2D dynamic programming

Security and privacy threats to on-chip non-volatile memories and countermeasures

Security engineering of nanostructures and nanomaterials

Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices

A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing

A new tightly-coupled transient electro-thermal simulation method for power electronics

A tensor-based volterra series black-box nonlinear system identification and simulation framework

Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation

Duplex: simultaneous parameter-performance exploration for optimizing analog circuits

Improved flop tray-based design implementation for power reduction

RC-aware global routing

Scalable, high-quality, SAT-based multi-layer escape routing

Redistribution layer routing for integrated fan-out wafer-level chip-scale packages

The architecture value engine: measuring and delivering sustainable SoC improvement

Circuit valorization in the IC design ecosystem

Interconnect-aware device targeting from PPA perspective

Measuring progress and value of IC implementation technology

Provably secure camouflaging strategy for IC protection

CamoPerturb: secure IC camouflaging for minterm protection

Chip editor: leveraging circuit edit for logic obfuscation and trusted fabrication

Arbitrary streaming permutations with minimum memory and latency

Multibank memory optimization for parallel data access in multiple data arrays

Allocation of multi-bit flip-flops in logic synthesis for power optimization

Model-based design of resource-efficient automotive control software

Testing automotive embedded systems under X-in-the-loop setups

Efficient statistical validation of machine learning systems for autonomous driving

CONVINCE: a cross-layer modeling, exploration and validation framework for next-generation connected vehicles

Overview of the 2016 CAD contest at ICCAD

ICCAD-2016 CAD contest in large-scale identical fault search

ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite

ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite

OpenDesign flow database: the infrastructure for VLSI design and design automation research

Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow

On detecting delay anomalies introduced by hardware trojans

An optimization-theoretic approach for attacking physical unclonable functions

LRR-DPUF: learning resilient and reliable digital physical unclonable function

Enabling online learning in lithography hotspot detection with information-theoretic feature optimization

Incorporating cut redistribution with mask assignment to enable 1D gridded design

VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology

DSA-compliant routing for two-dimensional patterns using block copolymer lithography

The art of semi-formal bug hunting

Compiled symbolic simulation for systemC

Exact diagnosis using boolean satisfiability

Efficient and accurate analysis of single event transients propagation using SMT-based techniques

Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper)

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration

Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms

The hype, myths, and realities of testing 3D integrated circuits

TASA: toolchain-agnostic static software randomisation for critical real-time systems

Splitting functions in code management on scratchpad memories

Adaptive performance prediction for integrated GPUs

Energy-efficient fault tolerance approach for internet of things applications

Critical path isolation for time-to-failure extension and lower voltage operation

Control synthesis and delay sensor deployment for efficient ASV designs

Performance driven routing for modern FPGAs

UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs

GPlace: a congestion-aware placement tool for ultrascale FPGAs

Resiliency in dynamically power managed designs

Dynamic reliability management for near-threshold dark silicon processors

A cross-layer approach for resiliency and energy efficiency in near threshold computing

Design space exploration of drone infrastructure for large-scale delivery services

Multi-objective design optimization for flexible hybrid electronics

KCAD: kinetic cyber-attack detection method for cyber-physical additive manufacturing systems

Autonomous sensor-context learning in dynamic human-centered internet-of-things environments

Formulating customized specifications for resource allocation problem of distributed embedded systems

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications

Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design

Architectural-space exploration of approximate multipliers

Design of power-efficient approximate multipliers for approximate artificial neural networks

Automated error prediction for approximate sequential circuits

Approximation-aware rewriting of AIGs for error tolerant applications

Properties first? a new design methodology for hardware, and its perspectives in safety analysis

Where formal verification can help in functional safety analysis

Formal approaches to design of active cell balancing architectures in battery management systems

How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?

A novel unified dummy fill insertion framework with SQP-based optimization method

Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells

Are proximity attacks a threat to the security of split manufacturing of integrated circuits?

Making split-fabrication more secure

A machine learning approach to fab-of-origin attestation

OpenRAM: an open-source memory compiler

A hardware-based technique for efficient implicit information flow tracking

Imprecise security: quality and complexity tradeoffs for hardware information flow tracking

Encasing block ciphers to foil key recovery attempts via side channel

Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect

Generation and use of statistical timing macro-models considering slew and load variability

TinySPICE plus: scaling up statistical SPICE simulations on GPU leveraging shared-memory based sparse matrix solution techniques

PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model

A fast layer elimination approach for power grid reduction

A deterministic approach to stochastic computation

Control-fluidic CoDesign for paper-based digital microfluidic biochips

Neural networks designing neural networks: multi-objective hyper-parameter optimization

Error recovery in a micro-electrode-dot-array digital microfluidic biochip?

Privacy protection via appliance scheduling in smart homes

Framework designs to enhance reliable and timely services of disaster management systems

Analysis of production data manipulation attacks in petroleum cyber-physical systems

Security challenges in smart surveillance systems and the solutions based on emerging nano-devices

Fast physics-based electromigration checking for on-die power grids

Exploring aging deceleration in FinFET-based multi-core systems

An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation

Voltage-based electromigration immortality check for general multi-branch interconnects

Exploiting randomness in sketching for efficient hardware implementation of machine learning applications

Making neural encoding robust and energy efficient: an advanced analog temporal encoder for brain-inspired computing systems

Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax

BugMD: automatic mismatch diagnosis for bug triaging

ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY

Delay-optimal technology mapping for in-memory computing using ReRAM devices

Reconfigurable in-memory computing with resistive memory crossbar

Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits

Approximation knob: power capping meets energy efficiency

IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods

BoostNoC: power efficient network-on-chip architecture for near threshold computing

QScale: thermally-efficient QoS management on heterogeneous mobile platforms

Synthesis of statically analyzable accelerator networks from sequential programs

Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory

Efficient synthesis of graph methods: a dynamically scheduled architecture

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools

SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs

From biochips to quantum circuits: computer-aided design for emerging technologies

Multilevel design understanding: from specification to logic invited paper

A flash-based digital circuit design flow

Content Provider	ACM Digital Library
Author	Khatri, Sunil P. Abusultan, Monther
Abstract	Traditionally, floating gate (flash) transistors have been used exclusively to implement non-volatile memory in its various forms. Recently, we showed that flash transistors can be used to implement digital circuits as well. In this paper, we present the details on the realization and characteristics of the block-level flash-based digital design. The current work describes the synthesis flow to decompose a circuit block into a network of interconnected FCs. The resulting network is characterized with respect to timing, power and energy, and the results are compared with a standard-cell based realization of the same block (obtained using commercial tools). We obtain significantly improved delay (0.59×), power (0.35×) and cell area (0.60×) compared to a traditional CMOS standard-cell based approach, when averaged over 12 standard benchmarks. It is generally rare that a circuit methodology yields results that are better than existing commercial standard-cell based flows in terms of delay, area, power and energy, and in this sense, we submit that our results are significant. Additional benefits of a flash-based digital design is that it allows for precision speed binning in the factory, and also enables in-field re-programmability (we note that our flash-based design is not an FPGA, but rather an ASIC style design) to counteract the speed degradation of a design due to aging. These benefits arise from the fact that the threshold voltage of flash devices can be controlled with precision.
Starting Page	1
Ending Page	6
Page Count	6
File Format	PDF
ISBN	9781450344661
DOI	10.1145/2966986.2966990
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-11-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Logic synthesis Flash-based circuits
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in