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A Fast Metal Layer Elimination Approach for Power Grid Reduction in Integrated Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | Najm, Farid N. |
| Copyright Year | 2016 |
| Abstract | A Fast Metal Layer Elimination Approach for Power Grid Reduction in Integrated Circuits Abdul-Amir Yassine Master of Applied Science Graduate Department of Electrical & Computer Engineering University of Toronto 2016 Simulation and verification of the on-die power delivery network (PDN) is one of the key steps in the design of integrated circuits. With the very large sizes of modern grids, verification of PDNs has become very expensive and a host of techniques for grid model approximation have been proposed. These include topological node elimination and full-blown numerical model order reduction (MOR). However, both of these traditional approaches suffer from drawbacks that limit their scalability to very large grids. In this thesis, we propose a novel technique for grid reduction that is a hybrid of both approaches – the method is numerical but also factors in grid topology. It works by eliminating whole internal layers of the grid at a time, while aiming to preserve the dynamic behavior of the grid. Effectively, instead of traditional node-by-node topological elimination we provide a numerical layer-by-layer block-matrix approach that is both fast and accurate. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://tspace.library.utoronto.ca/bitstream/1807/76202/3/Yassine_Abdul-Amir_201611_MAS_thesis.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Thesis |
