NDLI: Large-Memory Nodes for Energy Efficient High-Performance Computing

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Large-Memory Nodes for Energy Efficient High-Performance Computing

Write Locality and Optimization for Persistent Memory

Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories

Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache

Languages Must Expose Memory Heterogeneity

HAPPY: Hybrid Address-based Page Policy in DRAMs

Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip

Characterizing the Performance of Hybrid Memory Cube Using ApexMAP Application Probes

A New Metric to Measure Cache Utilization for HPC Workloads

Multi-Level Memory Policies: What You Add Is More Important Than What You Take Out

Co-DIMM: Inter-Socket Data Sharing via a Common DIMM Channel

Analyzing allocation behavior for multi-level memory

ConGen: An Application Specific DRAM Memory Controller Generator

AWARD: Approximation-aWAre Restore in Further Scaling DRAM

Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems

Evaluating the feasibility of storage class memory as main memory

Checkpointing Exascale Memory Systems with Existing Memory Technologies

DRAMPersist: Making DRAM Systems Persistent

Exploring Time and Energy for Complex Accesses to a Hybrid Memory Cube

Processing Acceleration with Resistive Memory-based Computation

Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud

DRAMScale: Mechanisms to Increase DRAM Capacity

Reliability and Performance Trade-off Study of Heterogeneous Memories

Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits

Exposing the Locality of Heterogeneous Memory Architectures to HPC Applications

Fast full system memory checkpointing with SSD-aware memory controller

Analyzing Consistency Issues in HMC Atomics

The Case for Associative DRAM Caches

Software Assisted Hardware Cache Coherence for Heterogeneous Processors

On the Use of DRAM with Unrepaired Weak Cells in Computing Systems

Integrated Thermal Analysis for Processing In Die-Stacking Memory

A Validation of DRAM RAPL Power Measurements

Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC

Challenges of Programming a System with Heterogeneous Memories and Heterogeneous Processors: A Programmer's View

Exploring Tag-Bit Memory Operations in Hybrid Memory Cubes

Prefetching as a Potentially Effective Technique for Hybrid Memory Optimization

Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging

CLARA: Circular Linked-List Auto and Self Refresh Architecture

TAPAS: Temperature-aware Adaptive Placement for 3D Stacked Hybrid Caches

Reverse Engineering of DRAMs: Row Hammer with Crosshair

Nswap2L: Transparently Managing Heterogeneous Cluster Storage Resources for Fast Swapping

Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems

Twin-Load: Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory Systems

Replacement Policies for Heterogeneous Memories

Data-Centric Computing Frontiers: A Survey On Processing-In-Memory

MicroRefresh: Minimizing Refresh Overhead in DRAM Caches

Low Latency, High Bisection-Bandwidth Networks for Exascale Memory Systems

Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture

How Many MLCs Should Impersonate SLCs to Optimize SSD Performance?

DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs

Large-Memory Nodes for Energy Efficient High-Performance Computing

Content Provider	ACM Digital Library
Author	Ayguadé, Eduard Carpenter, Paul M. Radulovic, Milan Zaragoza, David Radojković, Petar Zivanovic, Darko Strassburg, Janko Llort, Germán
Abstract	Energy consumption is by far the most important contributor to HPC cluster operational costs, and it accounts for a significant share of the total cost of ownership. Advanced energy-saving techniques in HPC components have received significant research and development effort, but a simple measure that can dramatically reduce energy consumption is often overlooked. We show that, in capacity computing, where many small to medium-sized jobs have to be solved at the lowest cost, a practical energy-saving approach is to scale-in the application on large-memory nodes. We evaluate scaling-in; i.e. decreasing the number of application processes and compute nodes (servers) to solve a fixed-sized problem, using a set of HPC applications running in a production system. Using standard-memory nodes, we obtain average energy savings of 36%, already a huge figure. We show that the main source of these energy savings is a decrease in the node-hours (node_hours = #nodes x exe_time), which is a consequence of the more efficient use of hardware resources. Scaling-in is limited by the per-node memory capacity. We therefore consider using large-memory nodes to enable a greater degree of scaling-in. We show that the additional energy savings, of up to 52%, mean that in many cases the investment in upgrading the hardware would be recovered in a typical system lifetime of less than five years.
Starting Page	3
Ending Page	9
Page Count	7
File Format	PDF
ISBN	9781450343053
DOI	10.1145/2989081.2989083
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-10-03
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Capacity computing Large-memory nodes High-performance computing Energy efficiency Scaling-in
Content Type	Text
Resource Type	Article

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