NDLI: System implications of integrated photonics

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System implications of integrated photonics

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Noninvasive leakage power tomography of integrated circuits by compressive sensing

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Power-efficient clustering via incomplete bypassing

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Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits

Variability of flip-flop timing at sub-threshold voltages

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System implications of integrated photonics

Content Provider	ACM Digital Library
Author	Jouppi, Norman P.
Abstract	Micron-scale photonic devices integrated with standard CMOS processes have the potential to dramatically increase system bandwidths, performance, and configuration flexibility while reducing system power. I first describe some recent developments in silicon nanophotonic technology, such as microring resonators. Small devices have many advantages: reduced power, increased density, and increased speed. By integrating many thousands of these devices on a chip, photonics could potentially be used for most high-speed off-chip and global on-chip communication. Integrated photonics has many advantages at the board and rack scale as well. Recent high-speed board-level electrical signaling (>2.5GHz) precludes the use of multi-drop busses or communication over long distances on ordinary inexpensive PC board materials. By using photonics, high fan-out and high-fan-in bus structures can be built. Due to the low loss of optical signals versus distance, these structures can even be distributed over rack-scale distances. This dramatically increases system flexibility while reducing interconnect power. As an example of the potential impact of photonics, I describe a system architecture for the 2017 time frame we call Corona. Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We believe that in comparison with an electrically-connected many-core alternative, Corona can provide 2 to 6 times more performance on many memory intensive workloads, while simultaneously significantly reducing power.
Starting Page	183
Ending Page	184
Page Count	2
File Format	PDF
ISBN	9781605581095
DOI	10.1145/1393921.1393923
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-08-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Interconnect Power Photonics
Content Type	Text
Resource Type	Article

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